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-rw-r--r--src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb45
-rw-r--r--src/mainboard/google/brox/variants/brox/overridetree.cb124
2 files changed, 149 insertions, 20 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index 42bf467b9a..23db754ca5 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -22,20 +22,26 @@ chip soc/intel/alderlake
# Enable CNVi BT
register "cnvi_bt_core" = "true"
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
-
- register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
- register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
- register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2 SD bridge
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC2)" # Type-A Port A1
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC1)" # Type-A Port A0
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI)
+ register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3 Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type A port A1
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3 Port
+
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Typc-C Port C0
+ register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable TCP1
+ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Typc-C Port C2
+ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -144,12 +150,11 @@ chip soc/intel/alderlake
}"
end
device ref dtt on end
-# device ref tbt_pcie_rp0 off end
-# device ref tbt_pcie_rp1 off end
-# device ref tbt_pcie_rp2 off end
-# device ref tcss_xhci on end
-# device ref tcss_dma0 on end
-# device ref tcss_dma1 on end
+ device ref tbt_pcie_rp0 on end
+ device ref tbt_pcie_rp2 on end
+ device ref tcss_xhci on end
+ device ref tcss_dma0 on end
+ device ref tcss_dma1 on end
device ref xhci on end
device ref shared_sram on end
device ref cnvi_wifi on
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index a5e2217fef..d7fc83ab78 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -1,4 +1,128 @@
chip soc/intel/alderlake
device domain 0 on
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C2 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C2 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 SD Bridge""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "has_power_resource" = "1"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A1 (DB)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+ device ref usb2_port7 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A0 (DCI)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
+ device ref usb2_port9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "has_power_resource" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A0 (DCI)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A1 (DB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+ device ref usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port1 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref tcss_dma1 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port3 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 03:51:30 +0000