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-rw-r--r--src/mainboard/google/auron/devicetree.cb2
-rw-r--r--src/mainboard/google/auron/variants/auron_paine/pei_data.c2
-rw-r--r--src/mainboard/google/auron/variants/auron_yuna/pei_data.c2
-rw-r--r--src/mainboard/google/auron/variants/buddy/overridetree.cb2
-rw-r--r--src/mainboard/google/auron/variants/buddy/pei_data.c2
-rw-r--r--src/mainboard/google/auron/variants/buddy/spd/spd.c1
-rw-r--r--src/mainboard/google/auron/variants/gandof/pei_data.c2
-rw-r--r--src/mainboard/google/auron/variants/lulu/pei_data.c2
-rw-r--r--src/mainboard/google/auron/variants/samus/pei_data.c2
-rw-r--r--src/mainboard/google/jecht/devicetree.cb2
-rw-r--r--src/mainboard/google/jecht/spd/spd.c1
-rw-r--r--src/mainboard/google/jecht/variants/guado/pei_data.c2
-rw-r--r--src/mainboard/google/jecht/variants/jecht/pei_data.c2
-rw-r--r--src/mainboard/google/jecht/variants/rikku/pei_data.c2
-rw-r--r--src/mainboard/google/jecht/variants/tidus/pei_data.c2
15 files changed, 6 insertions, 22 deletions
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 39c6554f1e..3e2f289145 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -12,6 +12,8 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
+ register "ec_present" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
register "s0ix_enable" = "1"
diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
index b157fcdf80..866ea3a56c 100644
--- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c
+++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
-
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
index b157fcdf80..866ea3a56c 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
+++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
-
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index ad8e50c4b6..75bf8ee20f 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -9,6 +9,8 @@ chip soc/intel/broadwell
.backlight_pwm_hz = 200,
}"
+ register "dq_pins_interleaved" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
register "s0ix_enable" = "0"
diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c
index fb9fc09a8c..e185d7ea79 100644
--- a/src/mainboard/google/auron/variants/buddy/pei_data.c
+++ b/src/mainboard/google/auron/variants/buddy/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
-
/* P0: Side USB3.0 port, USB3S1 */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_INTERNAL);
/* P1: Rear USB3.0 port, USB3R1 */
diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c
index 571aaafd33..78765148a6 100644
--- a/src/mainboard/google/auron/variants/buddy/spd/spd.c
+++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c
@@ -11,5 +11,4 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa4;
/* Enable 2x refresh mode */
pei_data->ddr_refresh_2x = 1;
- pei_data->dq_pins_interleaved = 1;
}
diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c
index b157fcdf80..866ea3a56c 100644
--- a/src/mainboard/google/auron/variants/gandof/pei_data.c
+++ b/src/mainboard/google/auron/variants/gandof/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
-
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c
index 663dd359e9..10862e8665 100644
--- a/src/mainboard/google/auron/variants/lulu/pei_data.c
+++ b/src/mainboard/google/auron/variants/lulu/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
-
/* P0: Port B, CN01 (IOBoard) */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_BACK_PANEL);
/* P1: Port A, CN01 */
diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c
index 4ef45ee10c..b0d9803622 100644
--- a/src/mainboard/google/auron/variants/samus/pei_data.c
+++ b/src/mainboard/google/auron/variants/samus/pei_data.c
@@ -18,8 +18,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{ 2, 0, 1, 3, 6, 4, 7, 5 },
{ 2, 1, 0, 3, 6, 5, 4, 7 } };
- pei_data->ec_present = 1;
-
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index e972baabaf..2f2fa4a443 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -9,6 +9,8 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
+ register "dq_pins_interleaved" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
device lapic 0 on end
diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c
index 6446a937e1..2a9f6b1920 100644
--- a/src/mainboard/google/jecht/spd/spd.c
+++ b/src/mainboard/google/jecht/spd/spd.c
@@ -10,5 +10,4 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa4;
// Enable 2x refresh mode
pei_data->ddr_refresh_2x = 1;
- pei_data->dq_pins_interleaved = 1;
}
diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c
index 3a00414d01..e8726993c7 100644
--- a/src/mainboard/google/jecht/variants/guado/pei_data.c
+++ b/src/mainboard/google/jecht/variants/guado/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
/* P0: VP8 */
pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE);
/* P1: Port A, CN22 */
diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c
index 3a00414d01..e8726993c7 100644
--- a/src/mainboard/google/jecht/variants/jecht/pei_data.c
+++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
/* P0: VP8 */
pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE);
/* P1: Port A, CN22 */
diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c
index 3a00414d01..e8726993c7 100644
--- a/src/mainboard/google/jecht/variants/rikku/pei_data.c
+++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
/* P0: VP8 */
pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE);
/* P1: Port A, CN22 */
diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c
index 566b9ad6ee..558d735864 100644
--- a/src/mainboard/google/jecht/variants/tidus/pei_data.c
+++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c
@@ -5,8 +5,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
/* P0: VP8 */
pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: Port 3, USB3 */