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-rw-r--r--src/mainboard/google/brya/variants/felwinter/Makefile.inc1
-rw-r--r--src/mainboard/google/brya/variants/felwinter/overridetree.cb14
-rw-r--r--src/mainboard/google/brya/variants/felwinter/variant.c13
3 files changed, 25 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/Makefile.inc b/src/mainboard/google/brya/variants/felwinter/Makefile.inc
index 8fe978f6ef..0256c73bb4 100644
--- a/src/mainboard/google/brya/variants/felwinter/Makefile.inc
+++ b/src/mainboard/google/brya/variants/felwinter/Makefile.inc
@@ -2,3 +2,4 @@
bootblock-y += gpio.c
ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 594cb6c614..0fa2e616d9 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -1,3 +1,11 @@
+fw_config
+ field DB_USB 0 2
+ option USB_ABSENT 0
+ option USB3_PS8815 1
+ option USB4_KB8001 2
+ end
+end
+
chip soc/intel/alderlake
register "SaGv" = "SaGv_Disabled"
@@ -7,8 +15,6 @@ chip soc/intel/alderlake
.configure_ext_fivr = 1,
}"
- register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A19, .pad_auxn_dc = GPP_A20}"
-
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb3_ports[3]" = "USB3_PORT_EMPTY"
@@ -48,7 +54,9 @@ chip soc/intel/alderlake
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port3 as dfp[0].typec_port
- device generic 0 on end
+ device generic 0 on
+ probe DB_USB USB4_KB8001
+ end
end
end
device ref pcie_rp8 on
diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c
new file mode 100644
index 0000000000..9234019952
--- /dev/null
+++ b/src/mainboard/google/brya/variants/felwinter/variant.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+ if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) {
+ config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19;
+ config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20;
+ }
+}