2 files changed, 24 insertions, 44 deletions

diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 559a86df88..50595cd769 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -193,6 +193,12 @@ static const struct soc_amd_gpio early_gpio_table[] = {
 	/* EN_PWR_WWAN_X */
 	PAD_GPO(GPIO_8, HIGH),
 
+/* Put WWAN into reset */
+	/* WWAN_RST_L */
+	PAD_GPO(GPIO_24, LOW),
+	/* WWAN_DISABLE */
+	PAD_GPO(GPIO_85, HIGH),
+
 /* Enable ESPI, GSC Interrupt & I2C Communication */
 	/* GSC_SOC_INT_L */
 	PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
@@ -246,13 +252,13 @@ static const struct soc_amd_gpio early_gpio_table[] = {
  */
 
 static const struct soc_amd_gpio bootblock_gpio_table[] = {
-	/* Enable WWAN & WLAN power, Deassert WWAN reset */
-	/* EN_PWR_WWAN_X */
-	PAD_GPO(GPIO_8, HIGH),
+	/* Enable WWAN, Deassert WWAN reset, keep WWAN PCIe Aux reset asserted */
 	/* WWAN_RST_L */
 	PAD_GPO(GPIO_24, HIGH),
 	/* WWAN_DISABLE */
 	PAD_GPO(GPIO_85, LOW),
+
+	/* Enable WLAN */
 	/* WLAN_DISABLE */
 	PAD_GPO(GPIO_130, LOW),
 };
@@ -264,14 +270,6 @@ static const struct soc_amd_gpio sleep_gpio_table[] = {
 
 /* PCIE_RST needs to be brought high before FSP-M runs */
 static const struct soc_amd_gpio pcie_gpio_table[] = {
-	/* Allow WWAN power to be overridden by platform */
-	/* EN_PWR_WWAN_X */
-	PAD_GPO(GPIO_8, HIGH),
-	/* WWAN_RST_L */
-	PAD_GPO(GPIO_24, HIGH),
-	/* WWAN_DISABLE */
-	PAD_GPO(GPIO_85, LOW),
-
 	/* Deassert all AUX_RESET lines & PCIE_RST */
 	/* WWAN_AUX_RESET_L */
 	PAD_GPO(GPIO_18, HIGH),
@@ -319,6 +317,7 @@ const struct soc_amd_gpio *__weak variant_override_gpio_table(size_t *size)
 
 const struct soc_amd_gpio * __weak variant_early_override_gpio_table(size_t *size)
 {
+	/* Note that when overriding this, board ID & CBI is not available */
 	*size = 0;
 	return NULL;
 }
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index b6c8eec8a0..08289c8bc9 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -8,7 +8,7 @@
 #include <baseboard/variants.h>
 
 /* This table is used by guybrush variant with board version < 2. */
-static const struct soc_amd_gpio bid1_gpio_table[] = {
+static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {
 	/* Unused TP183 */
 	PAD_NC(GPIO_31),
 	/* EN_SPKR */
@@ -21,41 +21,25 @@ static const struct soc_amd_gpio bid1_gpio_table[] = {
 
 /* This table is used by guybrush variant with board version < 2. */
 /* Use AUX Reset lines instead of PCIE_RST for Board Version 1 */
-static const struct soc_amd_gpio bid1_early_gpio_table[] = {
+static const struct soc_amd_gpio override_early_gpio_table[] = {
 	/* SD_AUX_RESET_L */
 	PAD_GPO(GPIO_70, LOW),
 };
 
 /* This table is used by guybrush variant with board version < 2. */
 static const struct soc_amd_gpio bid1_pcie_gpio_table[] = {
-	/* EN_PWR_WWAN_X */
-	PAD_GPO(GPIO_8, LOW),
-	/* WWAN_RST_L */
-	PAD_GPO(GPIO_24, LOW),
-	/* WWAN_DISABLE */
-	PAD_GPO(GPIO_85, HIGH),
 	/* SD_AUX_RESET_L */
 	PAD_GPO(GPIO_70, HIGH),
 };
 
-/* This table is used by guybrush variant with board version >= 2. */
-static const struct soc_amd_gpio bid2_pcie_gpio_table[] = {
-	/* EN_PWR_WWAN_X */
-	PAD_GPO(GPIO_8, LOW),
-	/* WWAN_RST_L */
-	PAD_GPO(GPIO_24, LOW),
-	/* WWAN_DISABLE */
-	PAD_GPO(GPIO_85, HIGH),
-};
-
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
 	uint32_t board_version = board_id();
 	*size = 0;
 
 	if (board_version < 2) {
-		*size = ARRAY_SIZE(bid1_gpio_table);
-		return bid1_gpio_table;
+		*size = ARRAY_SIZE(bid1_ramstage_gpio_table);
+		return bid1_ramstage_gpio_table;
 	}
 
 	return NULL;
@@ -63,27 +47,24 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 
 const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
 {
-	uint32_t board_version = board_id();
-	*size = 0;
-
-	if (board_version < 2) {
-		*size = ARRAY_SIZE(bid1_early_gpio_table);
-		return bid1_early_gpio_table;
-	}
-
-	return NULL;
+	/*
+	 * This code is run before the EC is available to check the board ID
+	 * since this is needed to work on Board ID 1 and is unused on other
+	 * versions of guybrush, just enable it.
+	 *
+	 * Guybrush BID>1: Unused TP27; BID==1: SD_AUX_RESET_L
+	 */
+	*size = ARRAY_SIZE(override_early_gpio_table);
+	return override_early_gpio_table;
 }
 
 const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
 {
 	uint32_t board_version = board_id();
 	*size = 0;
-
 	if (board_version < 2) {
 		*size = ARRAY_SIZE(bid1_pcie_gpio_table);
 		return bid1_pcie_gpio_table;
 	}
-
-	*size = ARRAY_SIZE(bid2_pcie_gpio_table);
-	return bid2_pcie_gpio_table;
+	return NULL;
 }