5 files changed, 79 insertions, 2 deletions
diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc
index 677b5f5ba7..2fe12a4ea1 100644
--- a/src/mainboard/google/rush_ryu/Makefile.inc
+++ b/src/mainboard/google/rush_ryu/Makefile.inc
@@ -32,7 +32,7 @@ bootblock-y += pmic.c
 bootblock-y += reset.c
 
 romstage-y += chromeos.c
-romstage-y += reset.c
+romstage-y += pmic.c
 romstage-y += reset.c
 romstage-y += romstage.c
 romstage-y += sdram_configs.c
diff --git a/src/mainboard/google/rush_ryu/gpio.h b/src/mainboard/google/rush_ryu/gpio.h
new file mode 100644
index 0000000000..532b92c85f
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/gpio.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
+#define __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
+
+#include <soc/nvidia/tegra132/gpio.h>
+
+/* LTE modem related GPIOs */
+enum {
+	MODEM_RESET	= GPIO(S3),
+	MODEM_PWR_ON	= GPIO(S4),
+	MDM_DET		= GPIO(V1),
+};
+
+#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ */
diff --git a/src/mainboard/google/rush_ryu/pmic.c b/src/mainboard/google/rush_ryu/pmic.c
index 8d5ea7aeec..85cc6e2f5b 100644
--- a/src/mainboard/google/rush_ryu/pmic.c
+++ b/src/mainboard/google/rush_ryu/pmic.c
@@ -45,7 +45,7 @@ static struct ti65913_init_reg init_list[] = {
 //etc.
 };
 
-static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
+void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
 {
 	if (i2c_writeb(bus, TI65913_I2C_ADDR, reg, val)) {
 		printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
diff --git a/src/mainboard/google/rush_ryu/pmic.h b/src/mainboard/google/rush_ryu/pmic.h
index 1f102a70c2..83afc4ecbe 100644
--- a/src/mainboard/google/rush_ryu/pmic.h
+++ b/src/mainboard/google/rush_ryu/pmic.h
@@ -20,6 +20,8 @@
 #ifndef __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__
 #define __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__
 
+#include <stdint.h>
+
 /* A44/Ryu has a TI 65913 PMIC */
 enum {
 	TI65913_SMPS12_CTRL = 0x20,
@@ -84,8 +86,13 @@ enum {
 
 	TI65913_LDO_SHORT_STATUS1 = 0x6D,
 	TI65913_LDO_SHORT_STATUS2 = 0x6E,
+
+	TI65913_CLK32KGAUDIO_CTRL = 0xD5,
+
+	TI65913_PRIMARY_SECONDARY_PAD2 = 0xFB,
 };
 
+void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay);
 void pmic_init(unsigned bus);
 
 #endif /* __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ */
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index 088357f4f2..4d22335fda 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <delay.h>
 #include <soc/addressmap.h>
 #include <soc/clock.h>
 #include <soc/funitcfg.h>
@@ -24,11 +25,20 @@
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/romstage.h>
 
+#include "gpio.h"
+#include "pmic.h"
+
 static const struct pad_config padcfgs[] = {
 	/* AP_SYS_RESET_L */
 	PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
 	/* WP_L */
 	PAD_CFG_GPIO_INPUT(KB_ROW1, PINMUX_PULL_NONE),
+	/* MODEM_RESET */
+	PAD_CFG_GPIO_OUT0(KB_ROW11, PINMUX_PULL_DOWN),
+	/* MODEM_PWR_ON */
+	PAD_CFG_GPIO_OUT0(KB_ROW12, PINMUX_PULL_DOWN),
+	/* MDM_DET - expected to be pulled down by LTE modem */
+	PAD_CFG_GPIO_INPUT(GPIO_PV1, PINMUX_PULL_UP),
 };
 
 static const struct pad_config tpm_pads[] = {
@@ -50,6 +60,32 @@ static const struct funit_cfg funits[] = {
 	FUNIT_CFG(I2C6, PLLP, 400, NULL, 0),
 };
 
+static void lte_modem_init(void)
+{
+	int mdm_det;
+
+	/* A LTE modem is present if MDM_DET is pulled down by the modem */
+	mdm_det = gpio_get_in_value(MDM_DET);
+	if (mdm_det == 1)
+		return;
+
+	printk(BIOS_DEBUG, "Found LTE modem\n");
+
+	/* Enable PMIC CLK32KGAUDIO to drive CLK_MDM_32K */
+	pmic_write_reg(I2CPWR_BUS, TI65913_PRIMARY_SECONDARY_PAD2, 0x02, 0);
+	pmic_write_reg(I2CPWR_BUS, TI65913_CLK32KGAUDIO_CTRL, 0x01, 0);
+
+	/* FULL_CARD_POWER_OFF# (A44: MODEM_PWR_ON) and RESET#
+	 * (A44: MODEM_RESET) of the LTE modem are actively low and initially
+	 * pulled down by the pad config. To properly enable the LTE modem,
+	 * de-assert FULL_CARD_POWER_OFF#, wait for at least 10ms, and then
+	 * de-assert RESET#.
+	 */
+	gpio_output(MODEM_PWR_ON, 1);
+	udelay(15000);
+	gpio_output(MODEM_RESET, 1);
+}
+
 void romstage_mainboard_init(void)
 {
 	/* Bring up controller interfaces for ramstage loading. */
@@ -63,6 +99,8 @@ void romstage_mainboard_init(void)
 	i2c_init(I2C2_BUS);
 	/* I2C6 bus (audio, etc.) */
 	i2c_init(I2C6_BUS);
+
+	lte_modem_init();
 }
 
 void mainboard_configure_pmc(void)