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-rw-r--r--src/mainboard/google/fizz/Kconfig9
-rw-r--r--src/mainboard/google/fizz/romstage.c11
2 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 377a13c773..2d2e6b78c0 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
select SOC_INTEL_KABYLAKE
+ select GENERIC_SPD_BIN
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -38,4 +39,12 @@ config MAINBOARD_FAMILY
config MAX_CPUS
int
default 8
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
endif
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index 8bcfcd3d44..be1d552156 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -15,6 +15,7 @@
#include <soc/romstage.h>
#include <string.h>
+#include <spd_bin.h>
#include <fsp/soc_binding.h>
@@ -28,4 +29,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
+
+ /* Read spd block to get memory config */
+ struct spd_block blk;
+ mem_cfg->DqPinsInterleaved = 1;
+ get_spd_smbus(&blk);
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+
+ dump_spd_info(&blk);
}