diff options
Diffstat (limited to 'src/mainboard/google/volteer/variants/volteer2')
-rw-r--r-- | src/mainboard/google/volteer/variants/volteer2/gpio.c | 5 | ||||
-rw-r--r-- | src/mainboard/google/volteer/variants/volteer2/overridetree.cb | 26 |
2 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 6c67fc216e..069b2f0a98 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -243,6 +243,11 @@ static const struct pad_config early_gpio_table[] = { /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), + + /* The two signals used for I2C communication with Ti50 on the + * volteer2_ti50 variant. */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */ }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index a36a8441b4..502883eee8 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -56,6 +56,32 @@ chip soc/intel/tigerlake register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM + # communication, that one needs early initialization. + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref dptf on chip drivers/intel/dptf |