diff options
Diffstat (limited to 'src/mainboard/google/veyron_rialto')
| -rw-r--r-- | src/mainboard/google/veyron_rialto/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_rialto/romstage.c | 2 |
2 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 40b5c39d2e..8393895e16 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -64,10 +64,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 1024 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index c18471abe5..f3883bd28f 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -113,7 +113,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); |