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+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_GOOGLE_VEYRON_JERRY
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ID_SUPPORT
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_SPI
+ select EC_SOFTWARE_SYNC
+ select SOC_ROCKCHIP_RK3288
+ select MAINBOARD_DO_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_CHROMEOS
+ select BOARD_ROMSIZE_KB_1024
+ select MAINBOARD_HAS_BOOTBLOCK_INIT
+ select HAVE_HARD_RESET
+ select RETURN_FROM_VERSTAGE
+
+config MAINBOARD_DIR
+ string
+ default google/veyron_jerry
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Veyron_Jerry"
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 0
+
+config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
+ int
+ default 100
+
+config VBOOT_RAMSTAGE_INDEX
+ hex
+ default 0x3
+
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 2
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x20
+
+config CONSOLE_SERIAL_UART_ADDRESS
+ hex
+ depends on CONSOLE_SERIAL_UART
+ default 0xFF690000
+
+endif # BOARD_GOOGLE_VEYRON_JERRY