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path: root/src/mainboard/google/stout/romstage.c
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Diffstat (limited to 'src/mainboard/google/stout/romstage.c')
-rw-r--r--src/mainboard/google/stout/romstage.c43
1 files changed, 42 insertions, 1 deletions
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 3d18f182b7..cb5b9c1b08 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -66,7 +66,48 @@ static void rcba_config(void)
{
u32 reg32;
- southbridge_configure_default_intmap();
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D20IP_XHCI XHCI INTA -> PIRQD (MSI)
+ * D26IP_E2P EHCI #2 INTA -> PIRQF
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ * D28IP_P2IP WLAN INTA -> PIRQD
+ * D28IP_P3IP Card Reader INTB -> PIRQE
+ * D28IP_P6IP LAN INTC -> PIRQB
+ * D29IP_E1P EHCI #1 INTA -> PIRQD
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+ (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+ (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
+ (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+ RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
+ DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);