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-rw-r--r--src/mainboard/google/rex/variants/kanix/overridetree.cb501
1 files changed, 499 insertions, 2 deletions
diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 6c284b305b..4e81a40f91 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -1,6 +1,503 @@
chip soc/intel/meteorlake
- device domain 0 on
- end
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
+
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
+ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1
+
+ # Enable eDP in Port A
+ register "ddi_port_A_config" = "1"
+ # Enable HDMI in Port B
+ register "ddi_port_B_config" = "0"
+
+ # Enable Display Port Configuration
+ register "ddi_ports_config" = "{
+ [DDI_PORT_A] = DDI_ENABLE_HPD,
+ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_1] = DDI_ENABLE_HPD,
+ [DDI_PORT_2] = DDI_ENABLE_HPD,
+ [DDI_PORT_3] = DDI_ENABLE_HPD,
+ [DDI_PORT_4] = DDI_ENABLE_HPD,
+ }"
+
+ register "serial_io_gspi_mode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ }"
+
+ register "serial_io_i2c_mode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| I2C0 | Audio and WFC |
+ #| I2C1 | Touchscreen |
+ #| I2C3 | Touchpad |
+ #| I2C4 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C5 | UFC, SAR1, SAR2, HPS |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 400,
+ .fall_time_ns = 350,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 600,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 600,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[4] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 550,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 900,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ }"
+
+ device domain 0 on
+ device ref igpu on
+ chip drivers/gfx/generic
+ register "device_count" = "6"
+ # DDIA for eDP
+ register "device[0].name" = ""LCD0""
+ register "device[0].type" = "panel"
+ # DDIB for HDMI
+ register "device[1].name" = ""DD01""
+ # TCP0 (DP-1) for port C0
+ register "device[2].name" = ""DD02""
+ register "device[2].use_pld" = "true"
+ register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ # TCP1 (DP-2) unused
+ register "device[3].name" = ""DD03""
+ # TCP2 (DP-3) for port C1
+ register "device[4].name" = ""DD04""
+ register "device[4].use_pld" = "true"
+ register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ # TCP3 (DP-4) unused
+ register "device[5].name" = ""DD05""
+ device generic 0 on end
+ end
+ end # Integrated Graphics Device
+ device ref dtt on
+ chip drivers/intel/dptf
+ ## sensor information
+ register "options.tsr[0].desc" = ""DDR_SOC""
+ register "options.tsr[1].desc" = ""Ambient""
+ register "options.tsr[2].desc" = ""Charger""
+
+ ## Active Policy
+ # FIXME: below values are initial reference values only
+ register "policies.active" = "{
+ [0] = {
+ .target = DPTF_TEMP_SENSOR_0,
+ .thresholds = {
+ TEMP_PCT(75, 90),
+ TEMP_PCT(70, 80),
+ TEMP_PCT(65, 70),
+ TEMP_PCT(60, 60),
+ TEMP_PCT(55, 50),
+ TEMP_PCT(50, 40),
+ TEMP_PCT(45, 30),
+ }
+ },
+ [1] = {
+ .target = DPTF_TEMP_SENSOR_1,
+ .thresholds = {
+ TEMP_PCT(75, 90),
+ TEMP_PCT(70, 80),
+ TEMP_PCT(65, 70),
+ TEMP_PCT(60, 60),
+ TEMP_PCT(55, 50),
+ TEMP_PCT(50, 40),
+ TEMP_PCT(45, 30),
+ }
+ },
+ [2] = {
+ .target = DPTF_TEMP_SENSOR_2,
+ .thresholds = {
+ TEMP_PCT(75, 90),
+ TEMP_PCT(70, 80),
+ TEMP_PCT(65, 70),
+ TEMP_PCT(60, 50),
+ }
+ }
+ }"
+
+ ## Passive Policy
+ # TODO: below values are initial reference values only
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
+ [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
+ }"
+
+ ## Critical Policy
+ # TODO: below values are initial reference values only
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+ }"
+
+ ## Power Limits Control
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 15000,
+ .max_power = 15000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,
+ },
+ .pl2 = {
+ .min_power = 57000,
+ .max_power = 57000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,
+ }
+ }"
+
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 3000 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }
+ }"
+
+ ## Fan Performance Control (Percent, Speed, Noise, Power)
+ register "controls.fan_perf" = "{
+ [0] = { 90, 6700, 220, 2200, },
+ [1] = { 80, 5800, 180, 1800, },
+ [2] = { 70, 5000, 145, 1450, },
+ [3] = { 60, 4900, 115, 1150, },
+ [4] = { 50, 3838, 90, 900, },
+ [5] = { 40, 2904, 55, 550, },
+ [6] = { 30, 2337, 30, 300, },
+ [7] = { 20, 1608, 15, 150, },
+ [8] = { 10, 800, 10, 100, },
+ [9] = { 0, 0, 0, 50, }
+ }"
+
+ ## Fan options
+ register "options.fan.fine_grained_control" = "1"
+ register "options.fan.step_size" = "2"
+
+ device generic 0 alias dptf_policy on end
+ end
+ end
+ device ref pcie_rp10 on
+ # Enable SSD Card PCIE 10 using clk 8
+ register "pcie_rp[PCIE_RP(10)]" = "{
+ .clk_src = 8,
+ .clk_req = 8,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
+ register "srcclk_pin" = "8"
+ device generic 0 on end
+ end
+ end # PCIE10 SSD card
+ device ref tbt_pcie_rp0 on end
+ device ref tbt_pcie_rp2 on end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C1 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
+ end
+ end
+ end
+ end
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+ use tcss_usb3_port0 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref tcss_dma1 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+ use tcss_usb3_port2 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C1 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A0 (DB)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+ device ref usb2_port9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A0 (DB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+ device ref usb3_port1 on end
+ end
+ end
+ end
+ end
+ device ref ipu on
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "0x50000"
+ register "acpi_name" = ""IPU0""
+ register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+ register "cio2_num_ports" = "1"
+ register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
+ register "cio2_lane_endpoint[0]" = ""^I2C5.CAM0""
+ register "cio2_prt[0]" = "4"
+ device generic 0 on end
+ end
+ end
+ device ref i2c0 on end #I2C0
+ device ref i2c1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN9004""
+ register "generic.desc" = ""ELAN Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)"
+ register "generic.detect" = "1"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C01)"
+ register "generic.reset_delay_ms" = "150"
+ register "generic.reset_off_delay_ms" = "1"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C00)"
+ register "generic.enable_delay_ms" = "6"
+ register "generic.enable_off_delay_ms" = "30"
+ register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
+ register "generic.stop_off_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 0x10 on end
+ end
+ end
+ device ref i2c3 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B00_IRQ)"
+ register "wake" = "GPE0_DW0_00"
+ register "detect" = "1"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PIXA2305""
+ register "generic.desc" = ""PIXA Touchpad""
+ register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B00_IRQ)"
+ register "generic.wake" = "GPE0_DW0_00"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 68 on end
+ end
+ end
+ device ref i2c4 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)"
+ device i2c 50 on end
+ end
+ end
+ device ref i2c5 on
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = ""INT3537""
+ register "acpi_uid" = "0"
+ register "acpi_name" = ""CAM0""
+ register "chip_name" = ""Hi-556 Camera""
+ register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+ register "has_power_resource" = "1"
+
+ register "ssdb.lanes_used" = "2"
+ register "ssdb.link_used" = "1"
+ register "num_freq_entries" = "1"
+ register "link_freq[0]" = "437 * MHz"
+ register "remote_name" = ""IPU0""
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_A11" #EN_UCAM_SENR_PWR
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_B09" #EN_FCAM_PWR
+ register "gpio_panel.gpio[2].gpio_num" = "GPP_V23" #UCAM_RST_L
+ register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+ register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+ #_ON
+ register "on_seq.ops_cnt" = "5"
+ register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+ register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+ register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "4"
+ register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+ device i2c 20 on end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+ register "acpi_uid" = "1"
+ register "acpi_name" = ""NVM0""
+ register "chip_name" = ""ST M24C64X""
+ register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+ register "nvm_size" = "0x2000"
+ register "nvm_pagesize" = "1"
+ register "nvm_readonly" = "1"
+ register "nvm_width" = "0x10"
+ register "nvm_compat" = ""atmel,24c64""
+
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+ register "has_power_resource" = "1"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_B09" #EN_FCAM_PWR
+
+ #_ON
+ register "on_seq.ops_cnt" = "1"
+ register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "1"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+ device i2c 50 on end
+ end
+ end #I2C5
+ device ref pcie_rp5 on
+ # Enable WLAN Card PCIE 5 using clk 5
+ register "pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_DW2_09"
+ register "add_acpi_dma_property" = "true"
+ use usb2_port10 as bluetooth_companion
+ device pci 00.0 on end
+ end
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E22)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F08)"
+ register "srcclk_pin" = "5"
+ device generic 0 on end
+ end
+ end #PCIE5 WLAN card
+ device ref gspi1 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)"
+ register "wake" = "GPE0_DW1_10"
+ register "has_power_resource" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+ register "enable_delay_ms" = "3"
+ device spi 0 on end
+ end # FPMCU
+ end
+ device ref soc_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port2 as usb2_port
+ use tcss_usb3_port0 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port2 as usb3_port
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end
+ device ref hda on end
+ end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 07:59:36 +0000