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-rw-r--r--src/mainboard/google/reef/variants/sand/devicetree.cb16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index 0735a35e10..a6692e6bf7 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -112,6 +112,22 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
+ # Override USB2 PER PORT register (PORT 1)
+ register "usb2eye[1]" = "{
+ .Usb20PerPortPeTxiSet = 4,
+ .Usb20PerPortTxiSet = 4,
+ .Usb20IUsbTxEmphasisEn = 1,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
+ # Override USB2 PER PORT register (PORT 4)
+ register "usb2eye[4]" = "{
+ .Usb20PerPortPeTxiSet = 7,
+ .Usb20PerPortTxiSet = 7,
+ .Usb20IUsbTxEmphasisEn = 1,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF