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-rw-r--r--src/mainboard/google/reef/acpi/chromeos.asl23
-rw-r--r--src/mainboard/google/reef/chromeos.c11
-rw-r--r--src/mainboard/google/reef/dsdt.asl1
-rw-r--r--src/mainboard/google/reef/mainboard.c2
4 files changed, 13 insertions, 24 deletions
diff --git a/src/mainboard/google/reef/acpi/chromeos.asl b/src/mainboard/google/reef/acpi/chromeos.asl
deleted file mode 100644
index bec6bcb80a..0000000000
--- a/src/mainboard/google/reef/acpi/chromeos.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio_defs.h>
-
-Name (OIPG, Package () {
- /* No physical recovery GPIO. */
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
- /* Firmware write protect GPIO. */
- Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
-})
diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c
index 4de6a70ce9..5c526dc6e4 100644
--- a/src/mainboard/google/reef/chromeos.c
+++ b/src/mainboard/google/reef/chromeos.c
@@ -19,6 +19,7 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/gpio.h>
#include "ec.h"
+#include "gpio.h"
#define GPIO_PCH_WP GPIO_75
#define GPIO_EC_IN_RW GPIO_41
@@ -69,3 +70,13 @@ int get_write_protect_state(void)
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+ CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 7a88fb648f..6243c72b15 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -38,7 +38,6 @@ DefinitionBlock(
}
/* Chrome OS specific */
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c
index def6900cf0..0c4ba8dc23 100644
--- a/src/mainboard/google/reef/mainboard.c
+++ b/src/mainboard/google/reef/mainboard.c
@@ -20,6 +20,7 @@
#include <nhlt.h>
#include <soc/gpio.h>
#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "gpio.h"
@@ -83,6 +84,7 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(device_t dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {