3 files changed, 49 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index e85d948b20..f0cf99fb97 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -239,8 +239,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
 	/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
 	PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
-	/* E15 : DDPD_HPD2 ==> NC */
-	PAD_CFG_NC(GPP_E15),
+	/* E15 : DDPD_HPD2 ==> PCH_MEM_CONFIG4 */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
         /* E16 : DDPE_HPD3 ==> PCH_GPP_E16 */
         PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT),
 	/* E17 : EDP_HPD ==> EDP_HPD */
diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
index 3dfe92f814..98450f602f 100644
--- a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
@@ -30,6 +30,7 @@
 #define GPIO_MEM_CONFIG_1	GPP_C13
 #define GPIO_MEM_CONFIG_2	GPP_C14
 #define GPIO_MEM_CONFIG_3	GPP_C15
+#define GPIO_MEM_CONFIG_4	GPP_E15
 
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c
index dec7626b73..6aa0e7610f 100644
--- a/src/mainboard/google/poppy/variants/nami/memory.c
+++ b/src/mainboard/google/poppy/variants/nami/memory.c
@@ -14,14 +14,32 @@
  */
 
 #include <baseboard/variants.h>
+#include <gpio.h>
+#include <variant/gpio.h>
 #include <string.h>
 
 /* Rcomp resistor */
 static const u16 rcomp_resistor_ddp[] = { 121, 81, 100 };
 static const u16 rcomp_resistor_sdp[] = { 200, 81, 100 };
+static const u16 rcomp_resistor_lpddr3[] = { 200, 81, 162 };
 
 /* Rcomp target */
 static const u16 rcomp_target[] = { 100, 40, 20, 20, 26 };
+static const u16 rcomp_target_lpddr3[] = { 100, 40, 40, 23, 40 };
+
+/* DQ byte map */
+static const u8 dq_map_lpddr3[][12] = {
+	{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+	  0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+	{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+	  0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }
+};
+
+/* DQS CPU<>DRAM map */
+static const u8 dqs_map_lpddr3[][8] = {
+	{ 1, 0, 3, 2, 6, 5, 4, 7 },
+	{ 0, 3, 2, 1, 6, 4, 7, 5 },
+};
 
 /* Memory ids are 1-indexed, so subtract 1 to use 0-indexed values in bitmap. */
 #define MEM_ID(x)	(1 << ((x) - 1))
@@ -29,10 +47,24 @@ static const u16 rcomp_target[] = { 100, 40, 20, 20, 26 };
 /* Bitmap to indicate which memory ids are using DDP. */
 static const uint16_t ddp_bitmap = MEM_ID(4);
 
-void variant_memory_params(struct memory_params *p)
+static void fill_lpddr3_memory_params(struct memory_params *p)
+{
+	p->type = MEMORY_LPDDR3;
+	p->use_sec_spd = 1;
+	p->dq_map = dq_map_lpddr3;
+	p->dq_map_size = sizeof(dq_map_lpddr3);
+	p->dqs_map = dqs_map_lpddr3;
+	p->dqs_map_size = sizeof(dqs_map_lpddr3);
+	p->rcomp_resistor = rcomp_resistor_lpddr3;
+	p->rcomp_resistor_size = sizeof(rcomp_resistor_lpddr3);
+	p->rcomp_target = rcomp_target_lpddr3;
+	p->rcomp_target_size = sizeof(rcomp_target_lpddr3);
+}
+
+static void fill_ddr4_memory_params(struct memory_params *p)
 {
-	memset(p, 0, sizeof(*p));
 	p->type = MEMORY_DDR4;
+	p->use_sec_spd = 0;
 
 	/* Rcomp resistor values are different for SDP and DDP. */
 	if (ddp_bitmap & MEM_ID(variant_memory_sku())) {
@@ -46,3 +78,15 @@ void variant_memory_params(struct memory_params *p)
 	p->rcomp_target = rcomp_target;
 	p->rcomp_target_size = sizeof(rcomp_target);
 }
+
+void variant_memory_params(struct memory_params *p)
+{
+	memset(p, 0, sizeof(*p));
+	gpio_input(GPIO_MEM_CONFIG_4);
+	if (gpio_get(GPIO_MEM_CONFIG_4))
+		/* set to LPDDR3 */
+		fill_lpddr3_memory_params(p);
+	else
+		/* default to DDR4 */
+		fill_ddr4_memory_params(p);
+}