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-rw-r--r--src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h6
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/Makefile.inc2
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/mainboard.c37
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/memory.c10
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/sku.c43
5 files changed, 77 insertions, 21 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
index 391f809c16..3c589713f3 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
@@ -54,6 +54,12 @@ struct memory_params {
const void *rcomp_target;
size_t rcomp_target_size;
bool use_sec_spd;
+
+ /* Enable SA overclocking mailbox commands */
+ bool enable_sa_oc_support;
+
+ /* The voltage offset applied to the SA in mV. 1000(mV) = Maximum */
+ uint16_t sa_voltage_offset_val;
};
void variant_memory_params(struct memory_params *p);
diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc
index d52893e50f..130c940aa2 100644
--- a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc
+++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc
@@ -7,9 +7,11 @@ bootblock-y += gpio.c
romstage-y += memory.c
romstage-y += gpio.c
+romstage-y += sku.c
ramstage-y += gpio.c
ramstage-y += nhlt.c
ramstage-y += mainboard.c
+ramstage-y += sku.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c
index e51370cfa3..b9f6314d1b 100644
--- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c
@@ -15,32 +15,16 @@
#include <baseboard/variants.h>
#include <chip.h>
-#include <gpio.h>
#include <device/device.h>
+#include <device/pci.h>
#include <smbios.h>
#include <string.h>
#include <variant/sku.h>
-uint32_t variant_board_sku(void)
-{
- static uint32_t sku_id = SKU_UNKNOWN;
-
- if (sku_id != SKU_UNKNOWN)
- return sku_id;
-
- /*
- * Nautilus uses GPP_B20 to determine SKU
- * 0 - Wifi SKU
- * 1 - LTE SKU
- */
- gpio_input_pulldown(GPP_B20);
- if (!gpio_get(GPP_B20))
- sku_id = SKU_0_NAUTILUS;
- else
- sku_id = SKU_1_NAUTILUS_LTE;
-
- return sku_id;
-}
+#define R_PCH_OC_WDT_CTL 0x54
+#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15
+#define B_PCH_OC_WDT_CTL_EN BIT14
+#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22
const char *smbios_mainboard_sku(void)
{
@@ -57,11 +41,22 @@ void variant_devtree_update(void)
uint32_t sku_id = variant_board_sku();
struct device *root = SA_DEV_ROOT;
config_t *cfg = root->chip_info;
+ uint16_t abase;
+ uint32_t val32;
switch (sku_id) {
case SKU_0_NAUTILUS:
/* Disable LTE module */
cfg->usb3_ports[3].enable = 0;
+
+ /* OC_WDT has been enabled in FSP-M by enabling SaOcSupport.
+ * We should clear it to prevent turning the system off. */
+ abase = pci_read_config16(PCH_DEV_PMC, ABASE) & 0xfffc;
+ val32 = inl(abase + R_PCH_OC_WDT_CTL);
+ val32 &= ~(B_PCH_OC_WDT_CTL_EN |
+ B_PCH_OC_WDT_CTL_FORCE_ALL |
+ B_PCH_OC_WDT_CTL_UNXP_RESET_STS);
+ outl(val32, abase + R_PCH_OC_WDT_CTL);
break;
case SKU_1_NAUTILUS_LTE:
diff --git a/src/mainboard/google/poppy/variants/nautilus/memory.c b/src/mainboard/google/poppy/variants/nautilus/memory.c
index dc845bcb7f..a0dd76bcb6 100644
--- a/src/mainboard/google/poppy/variants/nautilus/memory.c
+++ b/src/mainboard/google/poppy/variants/nautilus/memory.c
@@ -14,6 +14,7 @@
*/
#include <baseboard/variants.h>
+#include <variant/sku.h>
/* DQ byte map */
static const u8 dq_map[][12] = {
@@ -46,4 +47,13 @@ void variant_memory_params(struct memory_params *p)
p->rcomp_resistor_size = sizeof(rcomp_resistor);
p->rcomp_target = rcomp_target;
p->rcomp_target_size = sizeof(rcomp_target);
+
+ switch (variant_board_sku()) {
+ case SKU_0_NAUTILUS:
+ /* Bumping VCC_SA voltage offset 75mV to allow a
+ * tolerance to PLLGT on Nautilus-Wifi sku */
+ p->enable_sa_oc_support = 1;
+ p->sa_voltage_offset_val = 75;
+ break;
+ }
}
diff --git a/src/mainboard/google/poppy/variants/nautilus/sku.c b/src/mainboard/google/poppy/variants/nautilus/sku.c
new file mode 100644
index 0000000000..55b118d847
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nautilus/sku.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <variant/sku.h>
+
+uint32_t variant_board_sku(void)
+{
+#if ENV_ROMSTAGE
+ uint32_t sku_id = SKU_UNKNOWN;
+#else
+ static uint32_t sku_id = SKU_UNKNOWN;
+
+ if (sku_id != SKU_UNKNOWN)
+ return sku_id;
+#endif
+
+ /*
+ * Nautilus uses GPP_B20 to determine SKU
+ * 0 - Wifi SKU
+ * 1 - LTE SKU
+ */
+ gpio_input_pulldown(GPP_B20);
+ if (!gpio_get(GPP_B20))
+ sku_id = SKU_0_NAUTILUS;
+ else
+ sku_id = SKU_1_NAUTILUS_LTE;
+
+ return sku_id;
+}