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path: root/src/mainboard/google/poppy/variants/nautilus/gpio.c
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Diffstat (limited to 'src/mainboard/google/poppy/variants/nautilus/gpio.c')
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/gpio.c176
1 files changed, 88 insertions, 88 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c
index 555b532b2c..37378f93a7 100644
--- a/src/mainboard/google/poppy/variants/nautilus/gpio.c
+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c
@@ -9,25 +9,25 @@
/* Leave eSPI pins untouched from default settings */
static const struct pad_config gpio_table[] = {
/* A0 : RCIN# ==> NC(TP763) */
- PAD_CFG_NC(GPP_A0),
+ PAD_NC(GPP_A0, NONE),
/* A1 : ESPI_IO0 */
/* A2 : ESPI_IO1 */
/* A3 : ESPI_IO2 */
/* A4 : ESPI_IO3 */
/* A5 : ESPI_CS# */
/* A6 : SERIRQ ==> NC(TP764) */
- PAD_CFG_NC(GPP_A6),
+ PAD_NC(GPP_A6, NONE),
/* A7 : PIRQA# ==> NC(TP703) */
- PAD_CFG_NC(GPP_A7),
+ PAD_NC(GPP_A7, NONE),
/* A8 : CLKRUN# ==> NC(TP758)) */
- PAD_CFG_NC(GPP_A8),
+ PAD_NC(GPP_A8, NONE),
/* A9 : ESPI_CLK */
/* A10 : CLKOUT_LPC1 ==> NC */
- PAD_CFG_NC(GPP_A10),
+ PAD_NC(GPP_A10, NONE),
/* A11 : PME# ==> NC(TP726) */
- PAD_CFG_NC(GPP_A11),
+ PAD_NC(GPP_A11, NONE),
/* A12 : BM_BUSY# ==> NC */
- PAD_CFG_NC(GPP_A12),
+ PAD_NC(GPP_A12, NONE),
/* A13 : SUSWARN# ==> SUSWARN_L */
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* A14 : ESPI_RESET# */
@@ -38,81 +38,81 @@ static const struct pad_config gpio_table[] = {
/* A17 : SD_PWR_EN# ==> CPU1_SDCARD_PWREN_L */
PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* A19 : ISH_GP1 ==> NC */
- PAD_CFG_NC(GPP_A19),
+ PAD_NC(GPP_A19, NONE),
/* A20 : ISH_GP2 ==> NC */
- PAD_CFG_NC(GPP_A20),
+ PAD_NC(GPP_A20, NONE),
/* A21 : ISH_GP3 ==> CHP1_DIG_PDCT_L */
- PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_HIGH(GPP_A21, NONE, PLTRST),
/* A22 : ISH_GP4 ==> CHP1_DIG_IRQ_L */
- PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_HIGH(GPP_A22, NONE, PLTRST),
/* A23 : ISH_GP5 ==> CHP1_SPK_PA_EN */
PAD_CFG_GPO(GPP_A23, 1, DEEP),
/* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */
- PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT),
+ PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT),
/* B1 : CORE_VID1 ==> NC(TP722) */
- PAD_CFG_NC(GPP_B1),
+ PAD_NC(GPP_B1, NONE),
/* B2 : VRALERT# ==> NC */
- PAD_CFG_NC(GPP_B2),
+ PAD_NC(GPP_B2, NONE),
/* B3 : CPU_GP2 ==> CHP3_TP_INT_L */
- PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST),
/* B4 : CPU_GP3 ==> NC */
- PAD_CFG_NC(GPP_B4),
+ PAD_NC(GPP_B4, NONE),
/* B5 : SRCCLKREQ0# ==> CHP3_TP_INT_L - for wake event */
- PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT),
+ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT),
/* B6 : SRCCLKREQ1# ==> CHP3_WLAN_CLKREQ_L */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* B7 : SRCCLKREQ2# ==> NC */
- PAD_CFG_NC(GPP_B7),
+ PAD_NC(GPP_B7, NONE),
/* B8 : SRCCLKREQ3# ==> CHP3_WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, DEEP),
/* B9 : SRCCLKREQ4# ==> NC */
- PAD_CFG_NC(GPP_B9),
+ PAD_NC(GPP_B9, NONE),
/* B10 : SRCCLKREQ5# ==> NC */
- PAD_CFG_NC(GPP_B10),
+ PAD_NC(GPP_B10, NONE),
/* B11 : EXT_PWR_GATE# ==> NC */
- PAD_CFG_NC(GPP_B11),
+ PAD_NC(GPP_B11, NONE),
/* B12 : SLP_S0# ==> CHP3_SLPS0_L_ORG */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* B13 : PLTRST# ==> PLT3_RST_L */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* B14 : SPKR ==> NC */
- PAD_CFG_NC(GPP_B14),
+ PAD_NC(GPP_B14, NONE),
/* B15 : GSPI0_CS# ==> NC */
- PAD_CFG_NC(GPP_B15),
+ PAD_NC(GPP_B15, NONE),
/* B16 : GSPI0_CLK ==> NC */
- PAD_CFG_NC(GPP_B16),
+ PAD_NC(GPP_B16, NONE),
/* B17 : GSPI0_MISO ==> NC */
- PAD_CFG_NC(GPP_B17),
+ PAD_NC(GPP_B17, NONE),
/* B18 : GSPI0_MOSI ==> NC */
- PAD_CFG_NC(GPP_B18),
+ PAD_NC(GPP_B18, NONE),
/* B19 : GSPI1_CS# ==> CHP3_PEN_EJECT - for notification */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP),
/* B20 : GSPI1_CLK ==> LTE3_STRAP# - for SAR sensor presence */
- PAD_CFG_GPI(GPP_B20, 20K_PD, DEEP),
+ PAD_CFG_GPI(GPP_B20, DN_20K, DEEP),
/* B21 : GSPI1_MISO ==> CHP3_PEN_EJECT - for wake event */
- PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE),
+ PAD_CFG_GPI_SCI(GPP_B21, NONE, DEEP, EDGE_SINGLE, NONE),
/* B22 : GSPI1_MOSI ==> NC */
- PAD_CFG_NC(GPP_B22),
+ PAD_NC(GPP_B22, NONE),
/* B23 : SM1ALERT# ==> NC */
- PAD_CFG_NC(GPP_B23),
+ PAD_NC(GPP_B23, NONE),
/* C0 : SMBCLK ==> CHP3_SMBCLK */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
/* C1 : SMBDATA ==> CHP3_SMBDATA */
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* C2 : SMBALERT# ==> NC */
- PAD_CFG_NC(GPP_C2),
+ PAD_NC(GPP_C2, NONE),
/* C3 : SML0CLK ==> NC */
- PAD_CFG_NC(GPP_C3),
+ PAD_NC(GPP_C3, NONE),
/* C4 : SML0DATA ==> NC */
- PAD_CFG_NC(GPP_C4),
+ PAD_NC(GPP_C4, NONE),
/* C5 : SML0ALERT# ==> NC */
- PAD_CFG_NC(GPP_C5),
+ PAD_NC(GPP_C5, NONE),
/* C6 : SM1CLK ==> CPU3_EC_IN_RW */
- PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
+ PAD_CFG_GPI(GPP_C6, UP_20K, DEEP),
/* C7 : SM1DATA ==> NC */
- PAD_CFG_NC(GPP_C7),
+ PAD_NC(GPP_C7, NONE),
/* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */
PAD_CFG_GPO(GPP_C8, 0, DEEP),
/* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */
@@ -144,38 +144,38 @@ static const struct pad_config gpio_table[] = {
/* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */
PAD_CFG_GPO(GPP_C22, 0, DEEP),
/* C23 : UART2_CTS# ==> CHP3_PCH_WP*/
- PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+ PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
/* D1 : SPI1_CLK ==> NC */
- PAD_CFG_NC(GPP_D1),
+ PAD_NC(GPP_D1, NONE),
/* D2 : SPI1_MISO ==> NC */
- PAD_CFG_NC(GPP_D2),
+ PAD_NC(GPP_D2, NONE),
/* D3 : SPI1_MOSI ==> NC */
- PAD_CFG_NC(GPP_D3),
+ PAD_NC(GPP_D3, NONE),
/* D4 : FASHTRIG ==> CHP1_VDD_CAM_CORE_EN */
- PAD_CFG_NC(GPP_D4),
+ PAD_NC(GPP_D4, NONE),
/* D5 : ISH_I2C0_SDA ==> CHP1_I2C_ISH_SENSOR_SDA */
PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
/* D6 : ISH_I2C0_SCL ==> CHP1_I2C_ISH_SENSOR_SCL */
PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),
/* D7 : ISH_I2C1_SDA ==> NC */
- PAD_CFG_NC(GPP_D7),
+ PAD_NC(GPP_D7, NONE),
/* D8 : ISH_I2C1_SCL ==> NC */
- PAD_CFG_NC(GPP_D8),
+ PAD_NC(GPP_D8, NONE),
/* D9 : ISH_SPI_CS# ==> CHP1_HEADSET_INT_L */
- PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP),
+ PAD_CFG_GPI_APIC_HIGH(GPP_D9, UP_20K, DEEP),
/* D10 : ISH_SPI_CLK ==> NC */
- PAD_CFG_NC(GPP_D10),
+ PAD_NC(GPP_D10, NONE),
/* D11 : ISH_SPI_MISO ==> NC */
- PAD_CFG_NC(GPP_D11),
+ PAD_NC(GPP_D11, NONE),
/* D12 : ISH_SPI_MOSI ==> NC */
- PAD_CFG_NC(GPP_D12),
+ PAD_NC(GPP_D12, NONE),
/* D13 : ISH_UART0_RXD ==> NC */
- PAD_CFG_NC(GPP_D13),
+ PAD_NC(GPP_D13, NONE),
/* D14 : ISH_UART0_TXD ==> NC */
- PAD_CFG_NC(GPP_D14),
+ PAD_NC(GPP_D14, NONE),
/* D15 : ISH_UART0_RTS# ==> NC */
- PAD_CFG_NC(GPP_D15),
+ PAD_NC(GPP_D15, NONE),
/* D17 : DMIC_CLK1 */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* D18 : DMIC_DATA1 */
@@ -190,51 +190,51 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */
- PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST),
/* E1 : SATAXPCIE1 ==> NC */
- PAD_CFG_NC(GPP_E1),
+ PAD_NC(GPP_E1, NONE),
/* E2 : SATAXPCIE2 ==> NC */
- PAD_CFG_NC(GPP_E2),
+ PAD_NC(GPP_E2, NONE),
/* E3 : CPU_GP0 ==> NC */
- PAD_CFG_NC(GPP_E3),
+ PAD_NC(GPP_E3, NONE),
/* E4 : SATA_DEVSLP0 ==> NC */
- PAD_CFG_NC(GPP_E4),
+ PAD_NC(GPP_E4, NONE),
/* E5 : SATA_DEVSLP1 ==> NC */
- PAD_CFG_NC(GPP_E5),
+ PAD_NC(GPP_E5, NONE),
/* E6 : SATA_DEVSLP2 ==> NC */
- PAD_CFG_NC(GPP_E6),
+ PAD_NC(GPP_E6, NONE),
/* E7 : CPU_GP1 ==> CHP3_TSP_INT_L */
- PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST),
/* E8 : SATALED# ==> NC */
- PAD_CFG_NC(GPP_E8),
+ PAD_NC(GPP_E8, NONE),
/* E9 : USB2_OCO# ==> USB3_C1_OC1_L */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* E10 : USB2_OC1# ==> USB3_C0_OC0_L */
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* E12 : USB2_OC3# ==> NC */
- PAD_CFG_NC(GPP_E12),
+ PAD_NC(GPP_E12, NONE),
/* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */
- PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1),
/* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */
- PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1),
/* E15 : DDPD_HPD2 ==> CPU3_SD_CD_L */
- PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
+ PAD_CFG_GPI(GPP_E15, UP_20K, DEEP),
/* E16 : DDPE_HPD3 ==> NC(TP766) */
- PAD_CFG_NC(GPP_E16),
+ PAD_NC(GPP_E16, NONE),
/* E17 : EDP_HPD */
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* E18 : DDPB_CTRLCLK ==> NC */
- PAD_CFG_NC(GPP_E18),
+ PAD_NC(GPP_E18, NONE),
/* E19 : DDPB_CTRLDATA ==> NC */
- PAD_CFG_NC(GPP_E19),
+ PAD_NC(GPP_E19, NONE),
/* E20 : DDPC_CTRLCLK ==> NC */
- PAD_CFG_NC(GPP_E20),
+ PAD_NC(GPP_E20, NONE),
/* E21 : DDPC_CTRLDATA ==> NC */
- PAD_CFG_NC(GPP_E21),
+ PAD_NC(GPP_E21, NONE),
/* E22 : DDPD_CTRLCLK ==> CHP1_CABC */
PAD_CFG_GPO(GPP_E22, 1, DEEP),
/* E23 : DDPD_CTRLDATA ==> NC */
- PAD_CFG_NC(GPP_E23),
+ PAD_NC(GPP_E23, NONE),
/* The next 4 pads are for bit banging the amplifiers, default to I2S */
/* F0 : I2S2_SCLK ==> CHP1_I2S2_SCLK_SPKR_R */
@@ -244,15 +244,15 @@ static const struct pad_config gpio_table[] = {
/* F2 : I2S2_TXD ==> CHP1_I2S2_PCH_TX_SPKR_RX_R */
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
/* F3 : I2S2_RXD ==> NC */
- PAD_CFG_NC(GPP_F3),
+ PAD_NC(GPP_F3, NONE),
/* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */
PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
/* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */
PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
/* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */
- PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F6, UP_5K, DEEP, NF1),
/* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */
- PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F7, UP_5K, DEEP, NF1),
/* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */
PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
/* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */
@@ -284,7 +284,7 @@ static const struct pad_config gpio_table[] = {
/* F22 : EMMC_CLK */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
/* F23 : RSVD ==> NC */
- PAD_CFG_NC(GPP_F23),
+ PAD_NC(GPP_F23, NONE),
/* G0 : SD_CMD */
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
@@ -301,7 +301,7 @@ static const struct pad_config gpio_table[] = {
/* G6 : SD_CLK */
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
/* G7 : SD_WP */
- PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
/* GPD0: BATLOW# ==> CHP3_BATLOW# */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
@@ -310,23 +310,23 @@ static const struct pad_config gpio_table[] = {
/* GPD2: LAN_WAKE# ==> KBC3_PCH_WAKE_L */
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
/* GPD3: PWRBTN# ==> KBC3_PWRBTN_L */
- PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
/* GPD4: SLP_S3# ==> CHP3_SLPS3_L */
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* GPD5: SLP_S4# ==> CHP3_SLPS4_L */
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
/* GPD6: SLP_A# ==> NC(TP725) */
- PAD_CFG_NC(GPD6),
+ PAD_NC(GPD6, NONE),
/* GPD7: RSVD ==> NC */
- PAD_CFG_NC(GPD7),
+ PAD_NC(GPD7, NONE),
/* GPD8: SUSCLK ==> CHP3_SUSCLK */
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* GPD9: SLP_WLAN# ==> NC(TP724) */
- PAD_CFG_NC(GPD9),
+ PAD_NC(GPD9, NONE),
/* GPD10: SLP_S5# ==> NC(TP742) */
- PAD_CFG_NC(GPD10),
+ PAD_NC(GPD10, NONE),
/* GPD11: LANPHYC ==> NC */
- PAD_CFG_NC(GPD11),
+ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in bootblock */
@@ -343,10 +343,10 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
/* C23 : UART2_CTS# ==> PCH_WP */
- PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+ PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
- PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST),
};
const struct pad_config *variant_gpio_table(size_t *num)
@@ -363,20 +363,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
static const struct pad_config nautilus_default_sku_gpio_table[] = {
/* A18 : ISH_GP0 ==> NC */
- PAD_CFG_NC(GPP_A18),
+ PAD_NC(GPP_A18, NONE),
/* D0 : SPI1_CS# ==> NC */
- PAD_CFG_NC(GPP_D0),
+ PAD_NC(GPP_D0, NONE),
/* D16 : ISH_UART0_CTS# ==> NC */
- PAD_CFG_NC(GPP_D16),
+ PAD_NC(GPP_D16, NONE),
/* D21 : SPI1_IO2 ==> NC */
- PAD_CFG_NC(GPP_D21),
+ PAD_NC(GPP_D21, NONE),
/* E11 : USB2_OC2# ==> USB2_P2_FAULT# */
- PAD_CFG_NF(GPP_E11, 5K_PU, DEEP, NF1),
+ PAD_CFG_NF(GPP_E11, UP_5K, DEEP, NF1),
};
static const struct pad_config lte_sku_gpio_table[] = {
/* A18 : ISH_GP0 ==> LTE1_P_SENSOR_INT_L */
- PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP),
+ PAD_CFG_GPI_APIC_HIGH(GPP_A18, NONE, DEEP),
/* D0 : SPI1_CS# ==> LTE_PWROFF# */
PAD_CFG_GPO(GPP_D0, 1, DEEP),
/* D16 : ISH_UART0_CTS# ==> LTE3_W_DISABLE# */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 02:19:39 +0000