diff options
Diffstat (limited to 'src/mainboard/google/poppy/variants/nautilus/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 39d7353f58..79bb5fbe27 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -167,16 +167,16 @@ chip soc/intel/skylake # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)" # Type-A Port register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config |