diff options
Diffstat (limited to 'src/mainboard/google/poppy/variants/nami/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nami/devicetree.cb | 100 |
1 files changed, 56 insertions, 44 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 0c4a8e8802..fdbe6ffc75 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -196,58 +196,73 @@ chip soc/intel/skylake # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 185, - .scl_hcnt = 90, - .sda_hold = 36, - }, - }" # Trackpad register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" - register "i2c[1]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 185, - .scl_hcnt = 90, - .sda_hold = 36, - }, - }" # Pen register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 185, - .scl_hcnt = 100, - .sda_hold = 36, - }, - }" # Audio register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .speed_config[0] = { + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Touchscreen | + #| I2C1 | Trackpad | + #| I2C2 | Pen | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { .speed = I2C_SPEED_FAST, - .scl_lcnt = 195, - .scl_hcnt = 90, - .sda_hold = 36, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 90, + .sda_hold = 36, + }, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 90, + .sda_hold = 36, + }, + .early_init = 1, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 100, + .sda_hold = 36, + }, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 195, + .scl_hcnt = 90, + .sda_hold = 36, + }, }, - }" - - # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM - # communication before memory is up. - register "gspi[0]" = "{ - .speed_mhz = 1, - .early_init = 1, }" # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -270,9 +285,6 @@ chip soc/intel/skylake register "tcc_offset" = "10" # TCC of 90C register "psys_pmax" = "101" - # Lock Down - register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" - # PCH Trip Temperature in degree C register "pch_trip_temp" = "75" |