2 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index d0230e26f1..827c18b4ca 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -311,7 +311,7 @@ static void mainboard_init(device_t dev)
 		.base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE,
 		.video_info = &dp_video_info,
 	};
-	void *fb_addr;
+	void *fb_addr = (void *)(get_fb_base_kb() * KiB);
 
 	gpio_init();
 
@@ -323,7 +323,6 @@ static void mainboard_init(device_t dev)
 	/* Disable USB3.0 PLL to save 250mW of power */
 	disable_usb30_pll();
 
-	fb_addr = cbmem_find(CBMEM_ID_CONSOLE);
 	set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
 
 	/*
@@ -350,6 +349,7 @@ static void mainboard_init(device_t dev)
 	// gpio_info();
 }
 
+#if !CONFIG_DYNAMIC_CBMEM
 void get_cbmem_table(uint64_t *base, uint64_t *size)
 {
 	*size = CONFIG_COREBOOT_TABLES_SIZE;
@@ -357,13 +357,16 @@ void get_cbmem_table(uint64_t *base, uint64_t *size)
 				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
 				CONFIG_COREBOOT_TABLES_SIZE;
 }
+#endif
 
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = &mainboard_init;
 
+#if !CONFIG_DYNAMIC_CBMEM
 	/* set up coreboot tables */
 	cbmem_initialize();
+#endif
 
 	/* set up dcache and MMU */
 	/* FIXME: this should happen via resource allocator */
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index b582f3e19d..255f292b8a 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -22,6 +22,7 @@
 
 #include <armv7.h>
 #include <cbfs.h>
+#include <cbmem.h>
 
 #include <arch/cache.h>
 #include <cpu/samsung/exynos5420/i2c.h>
@@ -270,6 +271,9 @@ void main(void)
 	/* if this is uncommented SPI will not work correctly. */
 	clock_set_rate(PERIPH_ID_SPI1, 50000000);
 	simple_spi_test();
+
+	cbmem_initialize_empty();
+
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
 	simple_spi_test();
 	stage_exit(entry);