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-rw-r--r--src/mainboard/google/octopus/variants/baseboard/devicetree.cb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 97bb69142d..1411a7c13d 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -29,7 +29,7 @@ chip soc/intel/apollolake
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
- register "gpe0_dw1" = "PMC_GPE_NW_63_32"
+ register "gpe0_dw1" = "PMC_GPE_N_63_32"
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
@@ -117,6 +117,7 @@ chip soc/intel/apollolake
device pci 12.0 off end # - SATA
device pci 13.0 on
chip drivers/intel/wifi
+ register "wake" = "GPE0_DW1_11"
device pci 00.0 on end
end
end # - PCIe-A 0 Onboard M2 Slot(Wifi)