diff options
Diffstat (limited to 'src/mainboard/google/nyan_blaze/romstage.c')
| -rw-r--r-- | src/mainboard/google/nyan_blaze/romstage.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index e44381f238..30278f9614 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -57,7 +57,8 @@ static void __attribute__((noinline)) romstage(void) /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, + DIV_ROUND_UP(REGION_SIZE(sram), MiB), DCACHE_WRITEBACK); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) @@ -70,7 +71,7 @@ static void __attribute__((noinline)) romstage(void) mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); /* * A watchdog reset only resets part of the system so it ends up in |