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-rw-r--r--src/mainboard/google/nyan_big/Kconfig107
-rw-r--r--src/mainboard/google/nyan_big/Makefile.inc38
-rw-r--r--src/mainboard/google/nyan_big/bct/Makefile.inc24
-rw-r--r--src/mainboard/google/nyan_big/bct/emmc.cfg13
-rw-r--r--src/mainboard/google/nyan_big/bct/odmdata.cfg1
-rw-r--r--src/mainboard/google/nyan_big/bct/sdram-792.cfg346
-rw-r--r--src/mainboard/google/nyan_big/bct/sdram-924.cfg346
-rw-r--r--src/mainboard/google/nyan_big/bct/spi.cfg16
-rw-r--r--src/mainboard/google/nyan_big/boardid.c38
-rw-r--r--src/mainboard/google/nyan_big/boardid.h27
-rw-r--r--src/mainboard/google/nyan_big/bootblock.c88
-rw-r--r--src/mainboard/google/nyan_big/chromeos.c99
-rw-r--r--src/mainboard/google/nyan_big/devicetree.cb80
-rw-r--r--src/mainboard/google/nyan_big/mainboard.c303
-rw-r--r--src/mainboard/google/nyan_big/pmic.c112
-rw-r--r--src/mainboard/google/nyan_big/pmic.h48
-rw-r--r--src/mainboard/google/nyan_big/romstage.c142
17 files changed, 1828 insertions, 0 deletions
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
new file mode 100644
index 0000000000..4973667a1d
--- /dev/null
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -0,0 +1,107 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_GOOGLE_NYAN_BIG
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SOC_NVIDIA_TEGRA124
+ select MAINBOARD_HAS_CHROMEOS
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_SPI
+ select MAINBOARD_HAS_BOOTBLOCK_INIT
+ select MAINBOARD_DO_NATIVE_VGA_INIT
+ select BOARD_ROMSIZE_KB_1024
+ select SPI_FLASH
+ select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
+
+
+config MAINBOARD_DIR
+ string
+ default google/nyan_big
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Nyan Big"
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+config DRAM_DMA_START
+ hex
+ default 0x90000000
+
+config DRAM_DMA_SIZE
+ hex
+ default 0x00100000
+
+choice
+ prompt "BCT boot media"
+ default NYAN_BIG_BCT_CFG_SPI
+ help
+ Which boot media to configure the BCT for.
+
+config NYAN_BIG_BCT_CFG_SPI
+ bool "SPI"
+ help
+ Configure the BCT for booting from SPI.
+
+config NYAN_BIG_BCT_CFG_EMMC
+ bool "eMMC"
+ help
+ Configure the BCT for booting from eMMC.
+
+endchoice
+
+config BOOT_MEDIA_SPI_BUS
+ int "SPI bus with boot media ROM"
+ range 1 6
+ depends on NYAN_BIG_BCT_CFG_SPI
+ default 4
+ help
+ Which SPI bus the boot media is connected to.
+
+config BOOT_MEDIA_SPI_CHIP_SELECT
+ int "Chip select for SPI boot media"
+ range 0 3
+ depends on NYAN_BIG_BCT_CFG_SPI
+ default 0
+ help
+ Which chip select to use for boot media.
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 1
+
+choice
+ prompt "BCT sdram configuration"
+ default NYAN_BIG_BCT_SDRAM_792
+ help
+ The SDRAM configuration to put in the BCT.
+
+config NYAN_BIG_BCT_SDRAM_792
+ bool "792 MHz"
+
+config NYAN_BIG_BCT_SDRAM_924
+ bool "924 MHz"
+
+endchoice
+
+endif # BOARD_GOOGLE_NYAN_BIG
diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc
new file mode 100644
index 0000000000..d4a8cdbfd4
--- /dev/null
+++ b/src/mainboard/google/nyan_big/Makefile.inc
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# Add a handler for BCT config files
+$(call add-special-class,bct-cfg)
+bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
+
+$(obj)/generated/bct.cfg:
+ @printf " CAT $(subst $(obj)/,,$(@))\n"
+ cat $^ > $@
+
+subdirs-y += bct
+
+bootblock-y += boardid.c
+bootblock-y += bootblock.c
+bootblock-y += pmic.c
+
+romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan_big/bct/Makefile.inc b/src/mainboard/google/nyan_big/bct/Makefile.inc
new file mode 100644
index 0000000000..65b87f04a9
--- /dev/null
+++ b/src/mainboard/google/nyan_big/bct/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg
+bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_SPI) += spi.cfg
+bct-cfg-y += odmdata.cfg
+bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_924) += sdram-924.cfg
+bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_792) += sdram-792.cfg
diff --git a/src/mainboard/google/nyan_big/bct/emmc.cfg b/src/mainboard/google/nyan_big/bct/emmc.cfg
new file mode 100644
index 0000000000..c93cf4685b
--- /dev/null
+++ b/src/mainboard/google/nyan_big/bct/emmc.cfg
@@ -0,0 +1,13 @@
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00350001;
+BlockSize = 0x00004000;
+PageSize = 0x00000200;
+PartitionSize = 0x01000000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;
diff --git a/src/mainboard/google/nyan_big/bct/odmdata.cfg b/src/mainboard/google/nyan_big/bct/odmdata.cfg
new file mode 100644
index 0000000000..d0ab2bf8fb
--- /dev/null
+++ b/src/mainboard/google/nyan_big/bct/odmdata.cfg
@@ -0,0 +1 @@
+OdmData = 0x80080000;
diff --git a/src/mainboard/google/nyan_big/bct/sdram-792.cfg b/src/mainboard/google/nyan_big/bct/sdram-792.cfg
new file mode 100644
index 0000000000..d4d96600a5
--- /dev/null
+++ b/src/mainboard/google/nyan_big/bct/sdram-792.cfg
@@ -0,0 +1,346 @@
+# CFG Version 07
+# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command:
+# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650
+# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg
+# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz)
+# bkv file: PM358/PM358_792MHz_emc_reg.txt
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMInputDivider = 0x00000001;
+SDRAM[0].PllMFeedbackDivider = 0x00000042;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].PllMSetupControl = 0x00000000;
+SDRAM[0].PllMSelectDiv2 = 0x00000000;
+SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
+SDRAM[0].PllMKCP = 0x00000000;
+SDRAM[0].PllMKVCO = 0x00000000;
+SDRAM[0].EmcBctSpare0 = 0x00000000;
+SDRAM[0].EmcBctSpare1 = 0x00000000;
+SDRAM[0].EmcBctSpare2 = 0x00000000;
+SDRAM[0].EmcBctSpare3 = 0x00000000;
+SDRAM[0].EmcBctSpare4 = 0x00000000;
+SDRAM[0].EmcBctSpare5 = 0x00000000;
+SDRAM[0].EmcBctSpare6 = 0x00000000;
+SDRAM[0].EmcBctSpare7 = 0x00000000;
+SDRAM[0].EmcBctSpare8 = 0x00000000;
+SDRAM[0].EmcBctSpare9 = 0x00000000;
+SDRAM[0].EmcBctSpare10 = 0x00000000;
+SDRAM[0].EmcBctSpare11 = 0x00000000;
+SDRAM[0].EmcClockSource = 0x80000000;
+SDRAM[0].EmcAutoCalInterval = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig = 0xa1430000;
+SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
+SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
+SDRAM[0].EmcAutoCalWait = 0x00000190;
+SDRAM[0].EmcAdrCfg = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000001;
+SDRAM[0].EmcPinExtraWait = 0x00000000;
+SDRAM[0].EmcTimingControlWait = 0x00000000;
+SDRAM[0].EmcRc = 0x00000025;
+SDRAM[0].EmcRfc = 0x000000cd;
+SDRAM[0].EmcRfcSlr = 0x00000000;
+SDRAM[0].EmcRas = 0x00000019;
+SDRAM[0].EmcRp = 0x0000000a;
+SDRAM[0].EmcR2r = 0x00000000;
+SDRAM[0].EmcW2w = 0x00000000;
+SDRAM[0].EmcR2w = 0x00000007;
+SDRAM[0].EmcW2r = 0x0000000d;
+SDRAM[0].EmcR2p = 0x00000004;
+SDRAM[0].EmcW2p = 0x00000013;
+SDRAM[0].EmcRdRcd = 0x0000000a;
+SDRAM[0].EmcWrRcd = 0x0000000a;
+SDRAM[0].EmcRrd = 0x00000003;
+SDRAM[0].EmcRext = 0x00000002;
+SDRAM[0].EmcWext = 0x00000000;
+SDRAM[0].EmcWdv = 0x00000006;
+SDRAM[0].EmcWdvMask = 0x00000006;
+SDRAM[0].EmcQUse = 0x0000000b;
+SDRAM[0].EmcQuseWidth = 0x00000002;
+SDRAM[0].EmcIbdly = 0x00000000;
+SDRAM[0].EmcEInput = 0x00000003;
+SDRAM[0].EmcEInputDuration = 0x0000000c;
+SDRAM[0].EmcPutermExtra = 0x00090000;
+SDRAM[0].EmcPutermWidth = 0x00000004;
+SDRAM[0].EmcPutermAdj = 0x00000000;
+SDRAM[0].EmcCdbCntl1 = 0x00000000;
+SDRAM[0].EmcCdbCntl2 = 0x00000000;
+SDRAM[0].EmcCdbCntl3 = 0x00000000;
+SDRAM[0].EmcQRst = 0x00000002;
+SDRAM[0].EmcQSafe = 0x00000011;
+SDRAM[0].EmcRdv = 0x00000017;
+SDRAM[0].EmcRdvMask = 0x00000019;
+SDRAM[0].EmcQpop = 0x0000000f;
+SDRAM[0].EmcCtt = 0x00000000;
+SDRAM[0].EmcCttDuration = 0x00000004;
+SDRAM[0].EmcRefresh = 0x000017eb;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000001;
+SDRAM[0].EmcAct2Pden = 0x00000000;
+SDRAM[0].EmcAr2Pden = 0x000000c7;
+SDRAM[0].EmcRw2Pden = 0x00000018;
+SDRAM[0].EmcTxsr = 0x000000d7;
+SDRAM[0].EmcTxsrDll = 0x00000200;
+SDRAM[0].EmcTcke = 0x00000005;
+SDRAM[0].EmcTckesr = 0x00000006;
+SDRAM[0].EmcTpd = 0x00000005;
+SDRAM[0].EmcTfaw = 0x0000001d;
+SDRAM[0].EmcTrpab = 0x00000000;
+SDRAM[0].EmcTClkStable = 0x00000008;
+SDRAM[0].EmcTClkStop = 0x00000008;
+SDRAM[0].EmcTRefBw = 0x0000182c;
+SDRAM[0].EmcFbioCfg5 = 0x104ab898;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcCfgRsv = 0xff00ff00;
+SDRAM[0].EmcMrs = 0x80001d71;
+SDRAM[0].EmcEmrs = 0x80100002;
+SDRAM[0].EmcEmrs2 = 0x80200018;
+SDRAM[0].EmcEmrs3 = 0x80300000;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrw4 = 0x00000000;
+SDRAM[0].EmcMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt = 0x00f7000e;
+SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e;
+SDRAM[0].EmcCfg = 0x73300000;
+SDRAM[0].EmcCfg2 = 0x0000089d;
+SDRAM[0].EmcCfgPipe = 0x000040a0;
+SDRAM[0].EmcDbg = 0x01000c00;
+SDRAM[0].EmcCmdQ = 0x10004408;
+SDRAM[0].EmcMc2EmcQ = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl = 0x80003025;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[0].EmcCfgDigDll = 0xe00701b1;
+SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[0].EmcDevSelect = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl = 0x00040000;
+SDRAM[0].EmcDllXformDqs0 = 0x00000008;
+SDRAM[0].EmcDllXformDqs1 = 0x00000008;
+SDRAM[0].EmcDllXformDqs2 = 0x00000008;
+SDRAM[0].EmcDllXformDqs3 = 0x00000008;
+SDRAM[0].EmcDllXformDqs4 = 0x00000008;
+SDRAM[0].EmcDllXformDqs5 = 0x00000008;
+SDRAM[0].EmcDllXformDqs6 = 0x00000008;
+SDRAM[0].EmcDllXformDqs7 = 0x00000008;
+SDRAM[0].EmcDllXformDqs8 = 0x00000008;
+SDRAM[0].EmcDllXformDqs9 = 0x00000008;
+SDRAM[0].EmcDllXformDqs10 = 0x00000008;
+SDRAM[0].EmcDllXformDqs11 = 0x00000008;
+SDRAM[0].EmcDllXformDqs12 = 0x00000008;
+SDRAM[0].EmcDllXformDqs13 = 0x00000008;
+SDRAM[0].EmcDllXformDqs14 = 0x00000008;
+SDRAM[0].EmcDllXformDqs15 = 0x00000008;
+SDRAM[0].EmcDllXformQUse0 = 0x00000000;
+SDRAM[0].EmcDllXformQUse1 = 0x00000000;
+SDRAM[0].EmcDllXformQUse2 = 0x00000000;
+SDRAM[0].EmcDllXformQUse3 = 0x00000000;
+SDRAM[0].EmcDllXformQUse4 = 0x00000000;
+SDRAM[0].EmcDllXformQUse5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse6 = 0x00000000;
+SDRAM[0].EmcDllXformQUse7 = 0x00000000;
+SDRAM[0].EmcDllXformAddr0 = 0x0000000e;
+SDRAM[0].EmcDllXformAddr1 = 0x0000000e;
+SDRAM[0].EmcDllXformAddr2 = 0x00000000;
+SDRAM[0].EmcDllXformAddr3 = 0x0000000e;
+SDRAM[0].EmcDllXformAddr4 = 0x00000000;
+SDRAM[0].EmcDllXformAddr5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse8 = 0x00000000;
+SDRAM[0].EmcDllXformQUse9 = 0x00000000;
+SDRAM[0].EmcDllXformQUse10 = 0x00000000;
+SDRAM[0].EmcDllXformQUse11 = 0x00000000;
+SDRAM[0].EmcDllXformQUse12 = 0x00000000;
+SDRAM[0].EmcDllXformQUse13 = 0x00000000;
+SDRAM[0].EmcDllXformQUse14 = 0x00000000;
+SDRAM[0].EmcDllXformQUse15 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
+SDRAM[0].EmcDllXformDq0 = 0x0000000b;
+SDRAM[0].EmcDllXformDq1 = 0x0000000b;
+SDRAM[0].EmcDllXformDq2 = 0x0000000b;
+SDRAM[0].EmcDllXformDq3 = 0x0000000b;
+SDRAM[0].EmcDllXformDq4 = 0x0000000b;
+SDRAM[0].EmcDllXformDq5 = 0x0000000b;
+SDRAM[0].EmcDllXformDq6 = 0x0000000b;
+SDRAM[0].EmcDllXformDq7 = 0x0000000b;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalInterval = 0x00020000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000042;
+SDRAM[0].EmcZcalMrwCmd = 0x80000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcZcalInitDev0 = 0x80000011;
+SDRAM[0].EmcZcalInitDev1 = 0x00000000;
+SDRAM[0].EmcZcalInitWait = 0x00000001;
+SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
+SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcMrsExtra = 0x80001d71;
+SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[0].EmcDdr2Wait = 0x00000000;
+SDRAM[0].EmcClkenOverride = 0x00000000;
+SDRAM[0].McDisExtraSnapLevels = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[0].PmcVddpSel = 0x00000002;
+SDRAM[0].PmcVddpSelWait = 0x00000002;
+SDRAM[0].PmcDdrPwr = 0x00000003;
+SDRAM[0].PmcDdrCfg = 0x00002002;
+SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
+SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
+SDRAM[0].PmcRegShort = 0x00000000;
+SDRAM[0].PmcNoIoPower = 0x00000000;
+SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
+SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
+SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
+SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820;
+SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800;
+SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
+SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707;
+SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
+SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
+SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff;
+SDRAM[0].EmcAcpdControl = 0x00000000;
+SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
+SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
+SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
+SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
+SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
+SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
+SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
+SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
+SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
+SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
+SDRAM[0].EmcDsrVttgenDrv = 0x0505003f;
+SDRAM[0].EmcTxdsrvttgen = 0x00000000;
+SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
+SDRAM[0].McEmemAdrCfg = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
+SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
+SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
+SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
+SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
+SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
+SDRAM[0].McEmemCfg = 0x00000800;
+SDRAM[0].McEmemArbCfg = 0x0e00000b;
+SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
+SDRAM[0].McEmemArbTimingRcd = 0x00000004;
+SDRAM[0].McEmemArbTimingRp = 0x00000005;
+SDRAM[0].McEmemArbTimingRc = 0x00000013;
+SDRAM[0].McEmemArbTimingRas = 0x0000000c;
+SDRAM[0].McEmemArbTimingFaw = 0x0000000f;
+SDRAM[0].McEmemArbTimingRrd = 0x00000002;
+SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003;
+SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c;
+SDRAM[0].McEmemArbTimingR2R = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W = 0x00000005;
+SDRAM[0].McEmemArbTimingW2R = 0x00000008;
+SDRAM[0].McEmemArbDaTurns = 0x08050202;
+SDRAM[0].McEmemArbDaCovers = 0x00170e13;
+SDRAM[0].McEmemArbMisc0 = 0x736c2414;
+SDRAM[0].McEmemArbMisc1 = 0x70000f02;
+SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[0].McEmemArbOverride = 0x10000000;
+SDRAM[0].McEmemArbOverride1 = 0x00000000;
+SDRAM[0].McEmemArbRsv = 0xff00ff00;
+SDRAM[0].McClkenOverride = 0x00000000;
+SDRAM[0].McStatControl = 0x00000000;
+SDRAM[0].McDisplaySnapRing = 0x00000003;
+SDRAM[0].McVideoProtectBom = 0xfff00000;
+SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[0].McVideoProtectSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
+SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
+SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[0].McSecCarveoutBom = 0xfff00000;
+SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[0].EmcCaTrainingEnable = 0x00000000;
+SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
+SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
+SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
+SDRAM[0].BootRomPatchControl = 0x00000000;
+SDRAM[0].BootRomPatchData = 0x00000000;
+SDRAM[0].McMtsCarveoutBom = 0xfff00000;
+SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
+SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
+SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c;
diff --git a/src/mainboard/google/nyan_big/bct/sdram-924.cfg b/src/mainboard/google/nyan_big/bct/sdram-924.cfg
new file mode 100644
index 0000000000..fa3271a160
--- /dev/null
+++ b/src/mainboard/google/nyan_big/bct/sdram-924.cfg
@@ -0,0 +1,346 @@
+# CFG Version 11
+# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command:
+# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650
+# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg
+# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz)
+# bkv file: PM358/PM358_924MHz_emc_reg.txt
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMInputDivider = 0x00000001;
+SDRAM[0].PllMFeedbackDivider = 0x0000004d;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].PllMSetupControl = 0x00000000;
+SDRAM[0].PllMSelectDiv2 = 0x00000000;
+SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
+SDRAM[0].PllMKCP = 0x00000000;
+SDRAM[0].PllMKVCO = 0x00000000;
+SDRAM[0].EmcBctSpare0 = 0x00000000;
+SDRAM[0].EmcBctSpare1 = 0x00000000;
+SDRAM[0].EmcBctSpare2 = 0x00000000;
+SDRAM[0].EmcBctSpare3 = 0x00000000;
+SDRAM[0].EmcBctSpare4 = 0x00000000;
+SDRAM[0].EmcBctSpare5 = 0x00000000;
+SDRAM[0].EmcBctSpare6 = 0x00000000;
+SDRAM[0].EmcBctSpare7 = 0x00000000;
+SDRAM[0].EmcBctSpare8 = 0x00000000;
+SDRAM[0].EmcBctSpare9 = 0x00000000;
+SDRAM[0].EmcBctSpare10 = 0x00000000;
+SDRAM[0].EmcBctSpare11 = 0x00000000;
+SDRAM[0].EmcClockSource = 0x80000000;
+SDRAM[0].EmcAutoCalInterval = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig = 0xa1430404;
+SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
+SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
+SDRAM[0].EmcAutoCalWait = 0x00000190;
+SDRAM[0].EmcAdrCfg = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000001;
+SDRAM[0].EmcPinExtraWait = 0x00000000;
+SDRAM[0].EmcTimingControlWait = 0x00000000;
+SDRAM[0].EmcRc = 0x0000002b;
+SDRAM[0].EmcRfc = 0x000000ef;
+SDRAM[0].EmcRfcSlr = 0x00000000;
+SDRAM[0].EmcRas = 0x0000001e;
+SDRAM[0].EmcRp = 0x0000000b;
+SDRAM[0].EmcR2r = 0x00000000;
+SDRAM[0].EmcW2w = 0x00000000;
+SDRAM[0].EmcR2w = 0x00000008;
+SDRAM[0].EmcW2r = 0x0000000f;
+SDRAM[0].EmcR2p = 0x00000005;
+SDRAM[0].EmcW2p = 0x00000016;
+SDRAM[0].EmcRdRcd = 0x0000000b;
+SDRAM[0].EmcWrRcd = 0x0000000b;
+SDRAM[0].EmcRrd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000002;
+SDRAM[0].EmcWext = 0x00000000;
+SDRAM[0].EmcWdv = 0x00000006;
+SDRAM[0].EmcWdvMask = 0x00000006;
+SDRAM[0].EmcQUse = 0x0000000c;
+SDRAM[0].EmcQuseWidth = 0x00000002;
+SDRAM[0].EmcIbdly = 0x00000000;
+SDRAM[0].EmcEInput = 0x00000002;
+SDRAM[0].EmcEInputDuration = 0x0000000e;
+SDRAM[0].EmcPutermExtra = 0x000a0000;
+SDRAM[0].EmcPutermWidth = 0x00000004;
+SDRAM[0].EmcPutermAdj = 0x00000000;
+SDRAM[0].EmcCdbCntl1 = 0x00000000;
+SDRAM[0].EmcCdbCntl2 = 0x00000000;
+SDRAM[0].EmcCdbCntl3 = 0x00000000;
+SDRAM[0].EmcQRst = 0x00000001;
+SDRAM[0].EmcQSafe = 0x00000015;
+SDRAM[0].EmcRdv = 0x0000001b;
+SDRAM[0].EmcRdvMask = 0x0000001d;
+SDRAM[0].EmcQpop = 0x00000010;
+SDRAM[0].EmcCtt = 0x00000000;
+SDRAM[0].EmcCttDuration = 0x00000004;
+SDRAM[0].EmcRefresh = 0x00001be9;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa;
+SDRAM[0].EmcPdEx2Wr = 0x00000004;
+SDRAM[0].EmcPdEx2Rd = 0x00000015;
+SDRAM[0].EmcPChg2Pden = 0x00000001;
+SDRAM[0].EmcAct2Pden = 0x00000000;
+SDRAM[0].EmcAr2Pden = 0x000000e6;
+SDRAM[0].EmcRw2Pden = 0x0000001b;
+SDRAM[0].EmcTxsr = 0x000000fa;
+SDRAM[0].EmcTxsrDll = 0x00000200;
+SDRAM[0].EmcTcke = 0x00000006;
+SDRAM[0].EmcTckesr = 0x00000007;
+SDRAM[0].EmcTpd = 0x00000006;
+SDRAM[0].EmcTfaw = 0x00000022;
+SDRAM[0].EmcTrpab = 0x00000000;
+SDRAM[0].EmcTClkStable = 0x0000000a;
+SDRAM[0].EmcTClkStop = 0x0000000a;
+SDRAM[0].EmcTRefBw = 0x00001c29;
+SDRAM[0].EmcFbioCfg5 = 0x104ab898;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcCfgRsv = 0xff00ff00;
+SDRAM[0].EmcMrs = 0x80000f15;
+SDRAM[0].EmcEmrs = 0x80100002;
+SDRAM[0].EmcEmrs2 = 0x80200020;
+SDRAM[0].EmcEmrs3 = 0x80300000;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrw4 = 0x00000000;
+SDRAM[0].EmcMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt = 0x00ce000e;
+SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e;
+SDRAM[0].EmcCfg = 0x73300000;
+SDRAM[0].EmcCfg2 = 0x000008a5;
+SDRAM[0].EmcCfgPipe = 0x00000000;
+SDRAM[0].EmcDbg = 0x01000c00;
+SDRAM[0].EmcCmdQ = 0x10004408;
+SDRAM[0].EmcMc2EmcQ = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl = 0x800037ed;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[0].EmcCfgDigDll = 0xe00401b1;
+SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[0].EmcDevSelect = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl = 0x00040000;
+SDRAM[0].EmcDllXformDqs0 = 0x00000005;
+SDRAM[0].EmcDllXformDqs1 = 0x00000005;
+SDRAM[0].EmcDllXformDqs2 = 0x00000005;
+SDRAM[0].EmcDllXformDqs3 = 0x00000005;
+SDRAM[0].EmcDllXformDqs4 = 0x00000005;
+SDRAM[0].EmcDllXformDqs5 = 0x00000005;
+SDRAM[0].EmcDllXformDqs6 = 0x00000005;
+SDRAM[0].EmcDllXformDqs7 = 0x00000005;
+SDRAM[0].EmcDllXformDqs8 = 0x00000005;
+SDRAM[0].EmcDllXformDqs9 = 0x00000005;
+SDRAM[0].EmcDllXformDqs10 = 0x00000005;
+SDRAM[0].EmcDllXformDqs11 = 0x00000005;
+SDRAM[0].EmcDllXformDqs12 = 0x00000005;
+SDRAM[0].EmcDllXformDqs13 = 0x00000005;
+SDRAM[0].EmcDllXformDqs14 = 0x00000005;
+SDRAM[0].EmcDllXformDqs15 = 0x00000005;
+SDRAM[0].EmcDllXformQUse0 = 0x00000000;
+SDRAM[0].EmcDllXformQUse1 = 0x00000000;
+SDRAM[0].EmcDllXformQUse2 = 0x00000000;
+SDRAM[0].EmcDllXformQUse3 = 0x00000000;
+SDRAM[0].EmcDllXformQUse4 = 0x00000000;
+SDRAM[0].EmcDllXformQUse5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse6 = 0x00000000;
+SDRAM[0].EmcDllXformQUse7 = 0x00000000;
+SDRAM[0].EmcDllXformAddr0 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr1 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr2 = 0x00000000;
+SDRAM[0].EmcDllXformAddr3 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr4 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse8 = 0x00000000;
+SDRAM[0].EmcDllXformQUse9 = 0x00000000;
+SDRAM[0].EmcDllXformQUse10 = 0x00000000;
+SDRAM[0].EmcDllXformQUse11 = 0x00000000;
+SDRAM[0].EmcDllXformQUse12 = 0x00000000;
+SDRAM[0].EmcDllXformQUse13 = 0x00000000;
+SDRAM[0].EmcDllXformQUse14 = 0x00000000;
+SDRAM[0].EmcDllXformQUse15 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
+SDRAM[0].EmcDllXformDq0 = 0x00000006;
+SDRAM[0].EmcDllXformDq1 = 0x00000006;
+SDRAM[0].EmcDllXformDq2 = 0x00000006;
+SDRAM[0].EmcDllXformDq3 = 0x00000006;
+SDRAM[0].EmcDllXformDq4 = 0x00000006;
+SDRAM[0].EmcDllXformDq5 = 0x00000006;
+SDRAM[0].EmcDllXformDq6 = 0x00000006;
+SDRAM[0].EmcDllXformDq7 = 0x00000006;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalInterval = 0x00020000;
+SDRAM[0].EmcZcalWaitCnt = 0x0000004c;
+SDRAM[0].EmcZcalMrwCmd = 0x80000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcZcalInitDev0 = 0x80000011;
+SDRAM[0].EmcZcalInitDev1 = 0x00000000;
+SDRAM[0].EmcZcalInitWait = 0x00000001;
+SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
+SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcMrsExtra = 0x80000f15;
+SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[0].EmcDdr2Wait = 0x00000000;
+SDRAM[0].EmcClkenOverride = 0x00000000;
+SDRAM[0].McDisExtraSnapLevels = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[0].PmcVddpSel = 0x00000002;
+SDRAM[0].PmcVddpSelWait = 0x00000002;
+SDRAM[0].PmcDdrPwr = 0x00000003;
+SDRAM[0].PmcDdrCfg = 0x00002002;
+SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
+SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
+SDRAM[0].PmcRegShort = 0x00000000;
+SDRAM[0].PmcNoIoPower = 0x00000000;
+SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
+SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
+SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
+SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520;
+SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf;
+SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf;
+SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500;
+SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
+SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303;
+SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
+SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
+SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
+SDRAM[0].EmcAcpdControl = 0x00000000;
+SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
+SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
+SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
+SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
+SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
+SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
+SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
+SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
+SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
+SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
+SDRAM[0].EmcDsrVttgenDrv = 0x0606003f;
+SDRAM[0].EmcTxdsrvttgen = 0x00000000;
+SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
+SDRAM[0].McEmemAdrCfg = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
+SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
+SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
+SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
+SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
+SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
+SDRAM[0].McEmemCfg = 0x00000800;
+SDRAM[0].McEmemArbCfg = 0x0e00000d;
+SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
+SDRAM[0].McEmemArbTimingRcd = 0x00000005;
+SDRAM[0].McEmemArbTimingRp = 0x00000006;
+SDRAM[0].McEmemArbTimingRc = 0x00000016;
+SDRAM[0].McEmemArbTimingRas = 0x0000000e;
+SDRAM[0].McEmemArbTimingFaw = 0x00000011;
+SDRAM[0].McEmemArbTimingRrd = 0x00000002;
+SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004;
+SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e;
+SDRAM[0].McEmemArbTimingR2R = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W = 0x00000006;
+SDRAM[0].McEmemArbTimingW2R = 0x00000009;
+SDRAM[0].McEmemArbDaTurns = 0x09060202;
+SDRAM[0].McEmemArbDaCovers = 0x001a1016;
+SDRAM[0].McEmemArbMisc0 = 0x734e2a17;
+SDRAM[0].McEmemArbMisc1 = 0x70000f02;
+SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[0].McEmemArbOverride = 0x10000000;
+SDRAM[0].McEmemArbOverride1 = 0x00000000;
+SDRAM[0].McEmemArbRsv = 0xff00ff00;
+SDRAM[0].McClkenOverride = 0x00000000;
+SDRAM[0].McStatControl = 0x00000000;
+SDRAM[0].McDisplaySnapRing = 0x00000003;
+SDRAM[0].McVideoProtectBom = 0xfff00000;
+SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[0].McVideoProtectSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
+SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
+SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[0].McSecCarveoutBom = 0xfff00000;
+SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[0].EmcCaTrainingEnable = 0x00000000;
+SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
+SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
+SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
+SDRAM[0].BootRomPatchControl = 0x00000000;
+SDRAM[0].BootRomPatchData = 0x00000000;
+SDRAM[0].McMtsCarveoutBom = 0xfff00000;
+SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
+SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
+SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c;
diff --git a/src/mainboard/google/nyan_big/bct/spi.cfg b/src/mainboard/google/nyan_big/bct/spi.cfg
new file mode 100644
index 0000000000..aef7e82595
--- /dev/null
+++ b/src/mainboard/google/nyan_big/bct/spi.cfg
@@ -0,0 +1,16 @@
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00350001;
+BlockSize = 32768;
+PageSize = 2048;
+PartitionSize = 4194304;
+
+Bctcopy = 1;
+
+DevType[0] = NvBootDevType_Spi;
+DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
+
diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c
new file mode 100644
index 0000000000..f43e532c0a
--- /dev/null
+++ b/src/mainboard/google/nyan_big/boardid.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/nvidia/tegra124/gpio.h>
+
+#include "boardid.h"
+
+uint8_t board_id(void)
+{
+ static int id = -1;
+
+ if (id < 0) {
+ id = gpio_get_in_value(GPIO(Q3)) << 0 |
+ gpio_get_in_value(GPIO(T1)) << 1 |
+ gpio_get_in_value(GPIO(X1)) << 2 |
+ gpio_get_in_value(GPIO(X4)) << 3;
+ printk(BIOS_SPEW, "Board ID: %#x.\n", id);
+ }
+
+ return id;
+}
diff --git a/src/mainboard/google/nyan_big/boardid.h b/src/mainboard/google/nyan_big/boardid.h
new file mode 100644
index 0000000000..8b200326aa
--- /dev/null
+++ b/src/mainboard/google/nyan_big/boardid.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_BOARDID_H__
+#define __MAINBOARD_GOOGLE_NYAN_BIG_BOARDID_H__
+
+#include <stdint.h>
+
+uint8_t board_id(void);
+
+#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_BOARDID_H__ */
diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c
new file mode 100644
index 0000000000..f07951a059
--- /dev/null
+++ b/src/mainboard/google/nyan_big/bootblock.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra124/clk_rst.h>
+#include <soc/nvidia/tegra124/gpio.h>
+#include <soc/nvidia/tegra124/pinmux.h>
+#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
+
+#include "pmic.h"
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void set_clock_sources(void)
+{
+ /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
+ writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+
+ clock_configure_source(mselect, PLLP, 102000);
+
+ /* TODO: is the 1.333MHz correct? This may have always been bogus... */
+ clock_configure_source(i2c5, CLK_M, 1333);
+
+ /* TODO: We should be able to set this to 50MHz, but that did not seem
+ * reliable. */
+ clock_configure_source(sbc4, PLLP, 33333);
+}
+
+void bootblock_mainboard_init(void)
+{
+ set_clock_sources();
+
+ clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
+ CLK_H_I2C5 | CLK_H_APBDMA,
+ 0, CLK_V_MSELECT, 0, 0);
+
+ // Board ID GPIOs, bits 0-3.
+ gpio_input(GPIO(Q3));
+ gpio_input(GPIO(T1));
+ gpio_input(GPIO(X1));
+ gpio_input(GPIO(X4));
+
+ // I2C5 (PMU) clock.
+ pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
+ PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+ // I2C5 (PMU) data.
+ pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
+ PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+ i2c_init(4);
+ pmic_init(4);
+
+ /* SPI4 data out (MOSI) */
+ pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX,
+ PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 data in (MISO) */
+ pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX,
+ PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 clock */
+ pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX,
+ PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 chip select 0 */
+ pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX,
+ PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+
+ tegra_spi_init(4);
+}
diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c
new file mode 100644
index 0000000000..298fd6aea3
--- /dev/null
+++ b/src/mainboard/google/nyan_big/chromeos.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
+#include <soc/nvidia/tegra124/gpio.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ int count = 0;
+
+ /* Write Protect: active low */
+ gpios->gpios[count].port = GPIO_R1_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO(R1));
+ strncpy((char *)gpios->gpios[count].name, "write protect",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Recovery: active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "recovery",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Lid: active high */
+ gpios->gpios[count].port = GPIO_R4_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO(R4));
+ strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Power: active low */
+ gpios->gpios[count].port = GPIO_Q0_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0));
+ strncpy((char *)gpios->gpios[count].name, "power",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Developer: virtual GPIO active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "developer",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+ gpios->count = count;
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ uint32_t ec_events;
+
+ /* The GPIO is active low. */
+ if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO
+ return 1;
+
+ ec_events = google_chromeec_get_events_b();
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ return !gpio_get_in_value(GPIO(R1));
+}
diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb
new file mode 100644
index 0000000000..cb55b72b93
--- /dev/null
+++ b/src/mainboard/google/nyan_big/devicetree.cb
@@ -0,0 +1,80 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip soc/nvidia/tegra124
+ device cpu_cluster 0 on end
+# N.B. We ae not using the device tree in an effective way.
+# We need to change this in future such that the on-soc
+# devices are 'chips', which will allow us to go at them
+# in parallel. This is even easier on the ARM SOCs since there
+# are no single-access resources such as the infamous
+# cf8/cfc registers found on PCs.
+ register "display_controller" = "TEGRA_ARM_DISPLAYA"
+ register "xres" = "1366"
+ register "yres" = "768"
+ # this setting is what nvidia does; it makes no sense
+ # and does not agree with hardware. Why'd they do it?
+ register "framebuffer_bits_per_pixel" = "18"
+ register "cache_policy" = "DCACHE_WRITETHROUGH"
+
+ # With some help from the mainbaord designer
+ register "backlight_en_gpio" = "GPIO(H2)"
+ register "lvds_shutdown_gpio" = "0"
+ register "backlight_vdd_gpio" = "GPIO(P2)"
+ register "panel_vdd_gpio" = "0"
+ register "pwm" = "GPIO(H1)"
+
+# taken from u-boot; these look wrong however.
+ register "vdd_delay" = "400"
+ register "vdd_data_delay" = "4"
+ register "data_backlight_delay" = "203"
+ register "backlight_pwm_delay" = "17"
+ register "pwm_backlight_en_delay" = "15"
+
+# How to compute these: xrandr --verbose will give you this:
+#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
+# 2560 2608 2640 2720 hborder 0
+# 1700 1703 1713 1749 vborder 0
+#Then you can compute your values:
+#H front porch = 2608 - 2560 = 48
+#H sync = 2640 - 2608 = 32
+#H back porch = 2720 - 2640 = 80
+#V front porch = 1703 - 1700 = 3
+#V sync = 1713 - 1703 = 10
+#V back porch = 1749 - 1713 = 36
+#href_to_sync and vref_to_sync are from the vendor
+#this is just an example for a Pixel panel; other panels differ.
+# Here is a peppy panel:
+# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
+# h: width 1366 start 1502 end 1532 total 1592
+# v: height 768 start 776 end 788 total 800
+# These numbers were provided by Nvidia.
+ register "href_to_sync" = "1"
+ register "hfront_porch" = "44"
+ register "hsync_width" = "46"
+ register "hback_porch" = "44"
+
+ register "vref_to_sync" = "1"
+ register "vfront_porch" = "6"
+ register "vsync_width" = "8"
+ register "vback_porch" = "6"
+
+ # we *know* the pixel clock for this system.
+ register "pixel_clock" = "71"
+end
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
new file mode 100644
index 0000000000..4a05991726
--- /dev/null
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -0,0 +1,303 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <boot/coreboot_tables.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra124/clk_rst.h>
+#include <soc/nvidia/tegra124/gpio.h>
+#include <soc/nvidia/tegra124/mc.h>
+#include <soc/nvidia/tegra124/pmc.h>
+#include <soc/nvidia/tegra124/spi.h>
+#include <soc/nvidia/tegra124/usb.h>
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void set_clock_sources(void)
+{
+ clock_configure_source(i2c1, CLK_M, 1333);
+ clock_configure_source(i2c2, CLK_M, 1333);
+ clock_configure_source(i2c3, CLK_M, 1333);
+ clock_configure_source(i2c4, CLK_M, 1333);
+
+ clock_configure_source(sbc1, PLLP, 5000);
+
+ /*
+ * MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's
+ * maximum speed (48MHz) so we can change SDCLK by second stage divisor
+ * in payloads, without touching base clock.
+ */
+ clock_configure_source(sdmmc3, PLLP, 48000);
+ clock_configure_source(sdmmc4, PLLP, 48000);
+
+ /* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
+ * Note the source id of CLK_M for EXTPERIPH1 is 3. */
+ clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
+
+ /*
+ * I2S1 can use either PLLP or PLLA. Using PLLP is sufficient now since
+ * we only need 4.8MHz. Note the source id of PLLP for I2S is 4.
+ */
+ clock_configure_irregular_source(i2s1, PLLP, 4800, 4);
+
+ /* Note source id of PLLP for HOST1x is 4. */
+ clock_configure_irregular_source(host1x, PLLP, 408000, 4);
+
+ /* Use PLLD_OUT0 as clock source for disp1 */
+ clrsetbits_le32(&clk_rst->clk_src_disp1,
+ CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
+ 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
+
+}
+
+static void setup_pinmux(void)
+{
+ // Write protect.
+ gpio_input_pullup(GPIO(R1));
+ // Recovery mode.
+ gpio_input_pullup(GPIO(Q7));
+ // Lid switch.
+ gpio_input_pullup(GPIO(R4));
+ // Power switch.
+ gpio_input_pullup(GPIO(Q0));
+ // Developer mode.
+ gpio_input_pullup(GPIO(Q6));
+ // EC in RW.
+ gpio_input_pullup(GPIO(U4));
+
+ // SOC and TPM reset GPIO, active low.
+ gpio_output(GPIO(I5), 1);
+
+ // SPI1 MOSI
+ pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 MISO
+ pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 SCLK
+ pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 CS0
+ pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+
+ // I2C1 clock.
+ pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
+ PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+ // I2C1 data.
+ pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
+ PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+ // I2C2 clock.
+ pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
+ PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+ // I2C2 data.
+ pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
+ PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+ // I2C3 (cam) clock.
+ pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
+ PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+ // I2C3 (cam) data.
+ pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
+ PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+ // I2C4 (DDC) clock.
+ pinmux_set_config(PINMUX_DDC_SCL_INDEX,
+ PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
+ // I2C4 (DDC) data.
+ pinmux_set_config(PINMUX_DDC_SDA_INDEX,
+ PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
+
+ // TODO(hungte) Revice pinmux setup, make nice little SoC functions for
+ // every single logical thing instead of dumping a wall of code below.
+ uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE,
+ pin_up3 = (PINMUX_PULL_UP | PINMUX_INPUT_ENABLE |
+ PINMUX_TRISTATE),
+ pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE,
+ pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
+
+ // MMC3
+ pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX,
+ PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none);
+ pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX,
+ PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX,
+ PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX,
+ PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX,
+ PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX,
+ PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX,
+ PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up3);
+ pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX,
+ PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down);
+
+ // MMC3 Card Detect pin.
+ gpio_input_pullup(GPIO(V2));
+ // Enable MMC power.
+ gpio_output(GPIO(R0), 1);
+
+ // MMC4
+ pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX,
+ PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none);
+ pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX,
+ PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX,
+ PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX,
+ PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX,
+ PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX,
+ PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX,
+ PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX,
+ PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX,
+ PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
+ PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
+
+ /* We pull the USB VBUS signals up but keep them as inputs since the
+ * voltage source likes to drive them low on overcurrent conditions */
+ gpio_input_pullup(GPIO(N4)); /* USB VBUS EN0 */
+ gpio_input_pullup(GPIO(N5)); /* USB VBUS EN1 */
+
+ /* Clock output 1 (for external peripheral) */
+ pinmux_set_config(PINMUX_DAP_MCLK1_INDEX,
+ PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE);
+
+ /* I2S1 */
+ pinmux_set_config(PINMUX_DAP2_DIN_INDEX,
+ PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_TRISTATE |
+ PINMUX_INPUT_ENABLE);
+ pinmux_set_config(PINMUX_DAP2_DOUT_INDEX,
+ PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
+ pinmux_set_config(PINMUX_DAP2_FS_INDEX,
+ PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
+ pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
+ PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
+}
+
+static void setup_kernel_info(void)
+{
+ // Setup required information for Linux kernel.
+
+ // pmc.odmdata: [18:19]: console type, [15:17]: UART id.
+ // TODO(hungte) This should be done by filling BCT values, or derived
+ // from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
+ // value defined in BCT.
+ struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
+ writel(0x80080000, &pmc->odmdata);
+
+ // Not strictly info, but kernel graphics driver needs this region locked down
+ struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
+ writel(0, &mc->video_protect_bom);
+ writel(0, &mc->video_protect_size_mb);
+ writel(1, &mc->video_protect_reg_ctrl);
+}
+
+static void setup_ec_spi(void)
+{
+ struct tegra_spi_channel *spi;
+
+ spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+
+ /* Set frame header for use by CrOS EC */
+ spi->frame_header = 0xec;
+ spi->rx_frame_header_enable = 1;
+}
+
+static void mainboard_init(device_t dev)
+{
+ set_clock_sources();
+
+ clock_external_output(1); /* For external MAX98090 audio codec. */
+
+ /*
+ * Confirmed by NVIDIA hardware team, we need to take ALL audio devices
+ * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
+ * of reset and clock-enabled, otherwise reading AHUB devices (In our
+ * case, I2S/APBIF/AUDIO<XBAR>) will hang.
+ */
+ clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
+ CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
+ CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
+ CLK_L_HOST1X,
+
+ CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
+ CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
+
+ CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,
+
+ CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
+ CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
+ CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
+
+ CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
+
+ CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
+ CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
+ CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
+ CLK_X_AFC5);
+
+ usb_setup_utmip1();
+ /* USB2 is the camera, we don't need it in firmware */
+ usb_setup_utmip3();
+
+ setup_pinmux();
+
+ i2c_init(0);
+ i2c_init(1);
+ i2c_init(2);
+ i2c_init(3);
+
+ setup_kernel_info();
+ clock_init_arm_generic_timer();
+ setup_ec_spi();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "nyan_big",
+ .enable_dev = mainboard_enable,
+};
+
+void lb_board(struct lb_header *header)
+{
+ struct lb_range *dma;
+
+ dma = (struct lb_range *)lb_new_record(header);
+ dma->tag = LB_TAB_DMA;
+ dma->size = sizeof(*dma);
+ dma->range_start = CONFIG_DRAM_DMA_START;
+ dma->range_size = CONFIG_DRAM_DMA_SIZE;
+}
diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c
new file mode 100644
index 0000000000..f64b59c0ee
--- /dev/null
+++ b/src/mainboard/google/nyan_big/pmic.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "boardid.h"
+#include "pmic.h"
+
+enum {
+ AS3722_I2C_ADDR = 0x40
+};
+
+struct as3722_init_reg {
+ u8 reg;
+ u8 val;
+};
+
+static struct as3722_init_reg init_list[] = {
+ {AS3722_SDO0, 0x3C},
+ {AS3722_SDO1, 0x32},
+ {AS3722_SDO2, 0x3C},
+ {AS3722_SDO3, 0x00},
+ {AS3722_SDO4, 0x00},
+ {AS3722_SDO5, 0x50},
+ {AS3722_SDO6, 0x28},
+ {AS3722_LDO0, 0x8A},
+ {AS3722_LDO1, 0x00},
+ {AS3722_LDO2, 0x10},
+ {AS3722_LDO3, 0x59},
+ {AS3722_LDO4, 0x00},
+ {AS3722_LDO5, 0x00},
+ {AS3722_LDO6, 0x3F},
+ {AS3722_LDO7, 0x00},
+ {AS3722_LDO9, 0x00},
+ {AS3722_LDO10, 0x00},
+ {AS3722_LDO11, 0x00},
+};
+#define AS3722_INIT_REG_LEN ARRAY_SIZE(init_list)
+
+static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val)
+{
+ i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
+ udelay(10 * 1000);
+}
+
+static void pmic_slam_defaults(unsigned bus)
+{
+ int i;
+
+ for (i = 0; i < AS3722_INIT_REG_LEN; i++)
+ pmic_write_reg(bus, init_list[i].reg, init_list[i].val);
+}
+
+void pmic_init(unsigned bus)
+{
+ /*
+ * Don't need to set up VDD_CORE - already done - by OTP
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+ */
+
+ /* Restore PMIC POR defaults, in case kernel changed 'em */
+ pmic_slam_defaults(bus);
+
+ /* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
+ if (board_id() == 0)
+ pmic_write_reg(bus, 0x00, 0x3c);
+ else
+ pmic_write_reg(bus, 0x00, 0x50);
+
+ /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
+ pmic_write_reg(bus, 0x06, 0x28);
+
+ /* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
+ pmic_write_reg(bus, 0x12, 0x10);
+
+ /*
+ * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+ * First set it to bypass 3.3V straight thru, then enable the regulator
+ *
+ * NOTE: We do this early because doing it later seems to hose the CPU
+ * power rail/partition startup. Need to debug.
+ */
+ pmic_write_reg(bus, 0x16, 0x3f);
+
+ /*
+ * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
+ * the value (register 0x20 bit 4)
+ */
+ pmic_write_reg(bus, 0x0c, 0x07);
+ pmic_write_reg(bus, 0x20, 0x10);
+}
diff --git a/src/mainboard/google/nyan_big/pmic.h b/src/mainboard/google/nyan_big/pmic.h
new file mode 100644
index 0000000000..a64159908c
--- /dev/null
+++ b/src/mainboard/google/nyan_big/pmic.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__
+#define __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__
+
+enum {
+ AS3722_SDO0 = 0,
+ AS3722_SDO1,
+ AS3722_SDO2,
+ AS3722_SDO3,
+ AS3722_SDO4,
+ AS3722_SDO5,
+ AS3722_SDO6,
+
+ AS3722_LDO0 = 0x10,
+ AS3722_LDO1,
+ AS3722_LDO2,
+ AS3722_LDO3,
+ AS3722_LDO4,
+ AS3722_LDO5,
+ AS3722_LDO6,
+ AS3722_LDO7,
+
+ AS3722_LDO9 = 0x19,
+ AS3722_LDO10,
+ AS3722_LDO11,
+};
+
+void pmic_init(unsigned bus);
+
+#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__ */
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
new file mode 100644
index 0000000000..0e7102093d
--- /dev/null
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <arch/cpu.h>
+#include <arch/exception.h>
+#include <arch/stages.h>
+#include <device/device.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "soc/nvidia/tegra124/chip.h"
+#include <soc/display.h>
+#include <timestamp.h>
+
+// Convenient shorthand (in MB)
+#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
+#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
+#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
+
+enum {
+ L2CTLR_ECC_PARITY = 0x1 << 21,
+ L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
+ L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
+ L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
+ L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
+};
+
+enum {
+ L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
+ L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
+ L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
+};
+
+/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
+static void configure_l2ctlr(void)
+{
+ uint32_t val;
+
+ val = read_l2ctlr();
+ val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
+ val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
+ L2CTLR_ECC_PARITY);
+ write_l2ctlr(val);
+}
+
+/* Configures L2 Auxiliary Control Register for Cortex A15. */
+static void configure_l2actlr(void)
+{
+ uint32_t val;
+
+ val = read_l2actlr();
+ val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
+ L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
+ L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
+ write_l2actlr(val);
+}
+
+void main(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+ uint64_t romstage_start_time = timestamp_get();
+#endif
+
+ // Globally disable MMU, caches and branch prediction (these should
+ // already be disabled by default on reset).
+ uint32_t sctlr = read_sctlr();
+ sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
+ write_sctlr(sctlr);
+
+ arm_invalidate_caches();
+
+ // Renable icache and branch prediction.
+ sctlr = read_sctlr();
+ sctlr |= SCTLR_Z | SCTLR_I;
+ write_sctlr(sctlr);
+
+ configure_l2ctlr();
+ configure_l2actlr();
+
+ console_init();
+ exception_init();
+
+ mmu_init();
+ mmu_config_range(0, DRAM_START, DCACHE_OFF);
+ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
+ mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
+ CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
+ mmu_disable_range(0, 1);
+ dcache_invalidate_all();
+ dcache_mmu_enable();
+
+ /* For quality of the user experience, it's important to get
+ * the video going ASAP. Because there are long delays in some
+ * of the powerup steps, we do some very early setup here in
+ * romstage. The only thing setup_display does is manage
+ * 4 GPIOs, under control of the config struct members.
+ * In general, it is safe to enable panel power, and disable
+ * anything related to the backlight. If we get something wrong,
+ * we can easily fix it in ramstage by further GPIO manipulation,
+ * so we feel it is ok to do some setting at this point.
+ */
+
+ const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0);
+ printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc);
+ if (soc && soc->chip_info) {
+ const struct soc_nvidia_tegra124_config *config =
+ soc->chip_info;
+ setup_display((struct soc_nvidia_tegra124_config *)config);
+ }
+
+ cbmem_initialize_empty();
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(0);
+ timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
+ timestamp_add(TS_START_COPYRAM, timestamp_get());
+#endif
+ void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+ "fallback/coreboot_ram");
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_add(TS_END_COPYRAM, timestamp_get());
+#endif
+ stage_exit(entry);
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-20 00:34:27 +0000