diff options
Diffstat (limited to 'src/mainboard/google/nyan/bootblock.c')
| -rw-r--r-- | src/mainboard/google/nyan/bootblock.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index ca8eca42da..0761aedb7b 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -25,6 +25,7 @@ #include <soc/clock.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra124/clk_rst.h> +#include <soc/nvidia/tegra124/gpio.h> #include <soc/nvidia/tegra124/pinmux.h> #include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */ @@ -41,6 +42,10 @@ static void set_clock_sources(void) /* TODO: is the 1.333MHz correct? This may have always been bogus... */ clock_configure_source(i2c5, CLK_M, 1333); + + /* TODO: We should be able to set this to 50MHz, but that did not seem + * reliable. */ + clock_configure_source(sbc4, PLLP, 33333); } void bootblock_mainboard_init(void) @@ -49,7 +54,13 @@ void bootblock_mainboard_init(void) clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, CLK_H_I2C5 | CLK_H_APBDMA, - 0, CLK_V_MSELECT, 0); + 0, CLK_V_MSELECT, 0, 0); + + // Board ID GPIOs, bits 0-3. + gpio_input(GPIO(Q3)); + gpio_input(GPIO(T1)); + gpio_input(GPIO(X1)); + gpio_input(GPIO(X4)); // I2C5 (PMU) clock. pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, |