4 files changed, 5 insertions, 18 deletions
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index 8b42828533..d07e8514e3 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -19,6 +19,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
 #include "ec.h"
 #include <ec/google/chromeec/ec.h>
 
@@ -73,21 +74,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	device_t dev;
-#ifdef __PRE_RAM__
-	dev = PCI_DEV(0, 0x1f, 0);
-#else
-	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
-	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-	//u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
-
-	if (!gpio_base)
-		return -1;
-
-	u32 gp_lvl2 = inl(gpio_base + 0x38);
-
-	return (gp_lvl2 >> (57 - 32)) & 1;
+	return get_gpio(57);
 }
 
 int get_lid_switch(void)
diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c
index ea6110e8f9..dcd29a33c6 100644
--- a/src/mainboard/google/link/gpio.c
+++ b/src/mainboard/google/link/gpio.c
@@ -16,7 +16,7 @@
 #ifndef LINK_GPIO_H
 #define LINK_GPIO_H
 
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
 
 const struct pch_gpio_set1 pch_gpio_set1_mode = {
 	.gpio0 = GPIO_MODE_GPIO,  /* NMI_DBG# */
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 3e241d46c4..922061f6da 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -32,6 +32,7 @@
 #include "onboard.h"
 #include "ec.h"
 #include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
 #include <smbios.h>
 #include <device/pci.h>
 #include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 22b40a0f50..8142845bf2 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -30,8 +30,7 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
-#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
 #include "ec/google/chromeec/ec.h"
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>