summaryrefslogtreecommitdiff
path: root/src/mainboard/google/link
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/google/link')
-rw-r--r--src/mainboard/google/link/chromeos.c4
-rw-r--r--src/mainboard/google/link/mainboard_smi.c1
-rw-r--r--src/mainboard/google/link/romstage.c1
3 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index 04f68a9b1a..4ab5017f52 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -20,12 +20,8 @@
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <arch/io.h>
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
#include <device/device.h>
#include <device/pci.h>
-#endif
#include <southbridge/intel/bd82x6x/pch.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c
index 54cfb01f87..a4c4a50351 100644
--- a/src/mainboard/google/link/mainboard_smi.c
+++ b/src/mainboard/google/link/mainboard_smi.c
@@ -18,7 +18,6 @@
*/
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 689d2b52fa..f20a7226ab 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -24,7 +24,6 @@
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>