summaryrefslogtreecommitdiff
path: root/src/mainboard/google/kahlee
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/google/kahlee')
-rw-r--r--src/mainboard/google/kahlee/mainboard.c3
-rw-r--r--src/mainboard/google/kahlee/romstage.c3
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c3
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/gpio.c11
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/memory.c5
5 files changed, 15 insertions, 10 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index cd37c90f28..f1df8817e7 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -14,6 +14,7 @@
*/
#include <string.h>
+#include <compiler.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/acpi.h>
@@ -225,7 +226,7 @@ struct chip_operations mainboard_ops = {
};
/* Variants may override this function so see definitions in variants/ */
-uint8_t __attribute__((weak)) variant_board_sku(void)
+uint8_t __weak variant_board_sku(void)
{
return 0;
}
diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c
index 4cd2d40831..50e9931a73 100644
--- a/src/mainboard/google/kahlee/romstage.c
+++ b/src/mainboard/google/kahlee/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <compiler.h>
#include <amdblocks/dimm_spd.h>
#include <baseboard/variants.h>
#include <soc/romstage.h>
@@ -22,7 +23,7 @@ int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)
return variant_mainboard_read_spd(spdAddress, buf, len);
}
-void __attribute__((weak)) variant_romstage_entry(int s3_resume)
+void __weak variant_romstage_entry(int s3_resume)
{
/* By default, don't do anything */
}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index c9ce900e22..6ed516f7c6 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <compiler.h>
#include <amdblocks/agesawrapper.h>
#include <variant/gpio.h>
#include <boardid.h>
@@ -236,7 +237,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = {
*
**/
/*---------------------------------------------------------------------------*/
-VOID __attribute__((weak)) OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
+VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 8f4ba5c26f..cc75f29113 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <compiler.h>
#include <baseboard/variants.h>
#include <soc/gpio.h>
#include <soc/smi.h>
@@ -485,7 +486,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_GPI(GPIO_135, PULL_UP),
};
-const __attribute__((weak))
+const __weak
struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
{
if (board_id() < 2) {
@@ -497,7 +498,7 @@ struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
}
}
-const __attribute__((weak))
+const __weak
struct soc_amd_gpio *variant_gpio_table(size_t *size)
{
if (board_id() < 2) {
@@ -565,13 +566,13 @@ static const struct sci_source gpe_table[] = {
},
};
-const __attribute__((weak)) struct sci_source *get_gpe_table(size_t *num)
+const __weak struct sci_source *get_gpe_table(size_t *num)
{
*num = ARRAY_SIZE(gpe_table);
return gpe_table;
}
-int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map)
+int __weak variant_get_xhci_oc_map(uint16_t *map)
{
*map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0/4 = OC0 */
*map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1/5 = OC1 */
@@ -580,7 +581,7 @@ int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map)
return 0;
}
-int __attribute__((weak)) variant_get_ehci_oc_map(uint16_t *map)
+int __weak variant_get_ehci_oc_map(uint16_t *map)
{
*map = USB_OC_DISABLE_ALL;
return 0;
diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c
index b8ec917633..280140ba4d 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/memory.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c
@@ -14,13 +14,14 @@
*/
#include <baseboard/variants.h>
+#include <compiler.h>
#include <console/console.h>
#include <gpio.h> /* src/include/gpio.h */
#include <spd_bin.h>
#include <variant/gpio.h>
#include <amdblocks/dimm_spd.h>
-uint8_t __attribute__((weak)) variant_memory_sku(void)
+uint8_t __weak variant_memory_sku(void)
{
gpio_t pads[] = {
[3] = MEM_CONFIG3,
@@ -32,7 +33,7 @@ uint8_t __attribute__((weak)) variant_memory_sku(void)
return gpio_base2_value(pads, ARRAY_SIZE(pads));
}
-int __attribute__((weak)) variant_mainboard_read_spd(uint8_t spdAddress,
+int __weak variant_mainboard_read_spd(uint8_t spdAddress,
char *buf, size_t len)
{
struct region_device spd_rdev;