diff options
Diffstat (limited to 'src/mainboard/google/kahlee')
-rw-r--r-- | src/mainboard/google/kahlee/bootblock/bootblock.c | 7 | ||||
-rw-r--r-- | src/mainboard/google/kahlee/mainboard.c | 10 | ||||
-rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/gpio.c | 100 | ||||
-rw-r--r-- | src/mainboard/google/kahlee/variants/kahlee/gpio.c | 20 |
4 files changed, 33 insertions, 104 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index aac1d955d9..8f124b36ff 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -50,11 +50,4 @@ void bootblock_mainboard_init(void) /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); - - /* Configure cr50 interrupt pin for use in polling tpm status */ - if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) { - const uint32_t flags = GPIO_EDGE_TRIG | GPIO_ACTIVE_LOW | - GPIO_INT_STATUS_EN; - gpio_set_interrupt(H1_PCH_INT, flags); - } } diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index a01ae0acf5..e090401ddf 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -169,8 +169,16 @@ static void mainboard_init(void *chip_info) gpios = variant_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); + /* + * Some platforms use SCI not generated by a GPIO pin (event above 23). + * For these boards, gpe_configure_sci() is still needed, but all GPIO + * generated events (23-0) must be removed from gpe_table[]. + * For boards that only have GPIO generated events, table gpe_table[] + * must be removed, and get_gpe_table() should return NULL. + */ gpes = get_gpe_table(&num); - gpe_configure_sci(gpes, num); + if (gpes != NULL) + gpe_configure_sci(gpes, num); /* Initialize i2c busses that were not initialized in bootblock */ i2c_soc_init(); diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index ff6141e525..c7bd6a5be9 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -32,16 +32,17 @@ static const struct soc_amd_gpio gpio_set_stage_reset_old[] = { PAD_GPO(GPIO_4, HIGH), /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ - PAD_GPI(GPIO_6, PULL_UP), + PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW), /* GPIO_9 - H1_PCH_INT_ODL, SCI */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), + PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), /* GPIO_22 - EC_SCI_ODL, SCI */ - PAD_GPI(GPIO_22, PULL_UP), + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* GPIO_26 - APU_PCIE_RST_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), @@ -85,16 +86,17 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { PAD_GPO(GPIO_4, HIGH), /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ - PAD_GPI(GPIO_6, PULL_UP), + PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW), /* GPIO_9 - H1_PCH_INT_ODL, SCI */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), + PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), /* GPIO_22 - EC_SCI_ODL, SCI */ - PAD_GPI(GPIO_22, PULL_UP), + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* GPIO_24 - EC_PCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), @@ -150,7 +152,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram_old[] = { PAD_GPI(GPIO_3, PULL_UP), /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_5, PULL_UP), + PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW), /* GPIO_7 - APU_PWROK_OD (currently not used) */ PAD_GPI(GPIO_7, PULL_UP), @@ -162,7 +164,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram_old[] = { PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_11, PULL_UP), + PAD_SCI(GPIO_11, PULL_UP, EDGE_LOW), /* GPIO_12 - Unused (TP126) */ PAD_GPI(GPIO_12, PULL_UP), @@ -171,7 +173,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram_old[] = { PAD_GPI(GPIO_13, PULL_UP), /* GPIO_14 - APU_HP_INT_ODL, SCI */ - PAD_GPI(GPIO_14, PULL_UP), + PAD_SCI(GPIO_14, PULL_UP, EDGE_LOW), /* GPIO_16 - USB_C0_OC_L */ PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), @@ -189,7 +191,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram_old[] = { PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), /* GPIO_21 - APU_PEN_INT_ODL, SCI */ - PAD_GPI(GPIO_21, PULL_UP), + PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW), /* GPIO_24 - USB_A1_OC_ODL */ PAD_NF(GPIO_24, USB_OC3_L, PULL_UP), @@ -314,7 +316,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPI(GPIO_3, PULL_UP), /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_5, PULL_UP), + PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW), /* GPIO_7 - APU_PWROK_OD (currently not used) */ PAD_GPI(GPIO_7, PULL_UP), @@ -326,7 +328,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_11, PULL_UP), + PAD_SCI(GPIO_11, PULL_UP, EDGE_LOW), /* GPIO_12 - EN_PP3300_TRACKPAD */ PAD_GPO(GPIO_12, HIGH), @@ -335,7 +337,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPI(GPIO_13, PULL_UP), /* GPIO_14 - APU_HP_INT_ODL, SCI */ - PAD_GPI(GPIO_14, PULL_UP), + PAD_SCI(GPIO_14, PULL_UP, EDGE_LOW), /* GPIO_16 - USB_C0_OC_L */ PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), @@ -353,7 +355,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), /* GPIO_21 - APU_PEN_INT_ODL, SCI */ - PAD_GPI(GPIO_21, PULL_UP), + PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW), /* GPIO_25 - SD_CD */ PAD_NF(GPIO_25, SD0_CD, PULL_UP), @@ -486,73 +488,15 @@ struct soc_amd_gpio *variant_gpio_table(size_t *size) } /* - * GPE setup table must match ACPI GPE ASL - * { gevent, gpe, direction, level } + * This function is still needed for boards that sets gevents above 23 + * that will generate SCI or SMI, such as kahlee. Normally this function + * points to a table of gevents and what needs to be set. The code that + * calls it was modified so that when this function returns NULL then the + * caller does nothing. */ -static const struct sci_source gpe_table[] = { - - /* PCH_TRACKPAD_INT_3V3_ODL */ - { - .scimap = 7, - .gpe = 7, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - /* EC_PCH_WAKE_L */ - { - .scimap = EC_WAKE_GPI, - .gpe = EC_WAKE_GPI, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - /* H1_PCH_INT_ODL */ - { - .scimap = 22, - .gpe = 22, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - /* TOUCHSCREEN_INT_3V3_ODL */ - { - .scimap = 18, - .gpe = 18, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - - /* APU_HP_INT_ODL */ - { - .scimap = 6, - .gpe = 6, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - /* APU_PEN_INT_ODL */ - { - .scimap = 5, - .gpe = 5, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - /* EC_SCI_ODL */ - { - .scimap = 3, - .gpe = 3, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, -}; - const __weak struct sci_source *get_gpe_table(size_t *num) { - *num = ARRAY_SIZE(gpe_table); - return gpe_table; + return NULL; } int __weak variant_get_xhci_oc_map(uint16_t *map) diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index 8f30e4b40e..30723508db 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -26,7 +26,7 @@ */ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* AGPIO2, to become event generator */ - PAD_GPI(GPIO_2, PULL_UP), + PAD_SCI(GPIO_2, PULL_UP, EDGE_LOW), /* SER_TX */ PAD_NF(GPIO_8, SerPortTX_OUT, PULL_UP), @@ -44,7 +44,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), /* AGPIO22 EC_SCI */ - PAD_GPI(GPIO_22, PULL_UP), + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* SPI_TPM_CS_L */ PAD_NF(GPIO_76, SPI_TPM_CS_L, PULL_DOWN), @@ -120,22 +120,6 @@ const struct soc_amd_gpio *variant_gpio_table(size_t *size) */ static const struct sci_source gpe_table[] = { - /* EC AGPIO22/Gevent3 -> GPE 3 */ - { - .scimap = 3, - .gpe = 3, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - /* PCIE/WLAN AGPIO2/Gevent8 -> GPE8 */ - { - .scimap = 8, - .gpe = 8, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_LVL, - }, - /* EHCI USB_PME -> GPE24 */ { .scimap = 24, |