1 files changed, 0 insertions, 97 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index 6ed516f7c6..648329fbc4 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -129,98 +129,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 	.DdiLinkList  = (void *)DdiList
 };
 
-/*
- * TODO: Remove after we're done with Grunt Proto
- */
-static const PCIe_PORT_DESCRIPTOR PortListNoBayhub[] = {
-	/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortDisabled,		/* mPortPresent */
-				ChannelTypeExt6db,	/* mChannelType */
-				2,			/* mDevAddress */
-				1,			/* mDevFunction */
-				HotplugDisabled,	/* mHotplug */
-				PcieGenMaxSupported,	/* mMaxLinkSpeed */
-				PcieGenMaxSupported,	/* mMaxLinkCap */
-				AspmL0sL1,		/* mAspm */
-				0,			/* mResetId */
-				0)			/* mClkPmSupport */
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortEnabled,		/* mPortPresent */
-				ChannelTypeExt6db,	/* mChannelType */
-				2,			/* mDevAddress */
-				2,			/* mDevFunction */
-				HotplugDisabled,	/* mHotplug */
-				PcieGenMaxSupported,	/* mMaxLinkSpeed */
-				PcieGenMaxSupported,	/* mMaxLinkCap */
-				AspmL0sL1,		/* mAspm */
-				PCIE_0_RST,		/* mResetId */
-				0)			/* mClkPmSupport */
-	},
-	/* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortDisabled,		/* mPortPresent */
-				ChannelTypeExt6db,	/* mChannelType */
-				2,			/* mDevAddress */
-				3,			/* mDevFunction */
-				HotplugDisabled,	/* mHotplug */
-				PcieGenMaxSupported,	/* mMaxLinkSpeed */
-				PcieGenMaxSupported,	/* mMaxLinkCap */
-				AspmL0sL1,		/* mAspm */
-				PCIE_1_RST,		/* mResetId */
-				0)			/* mClkPmSupport */
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortDisabled,		/* mPortPresent */
-				ChannelTypeExt6db,	/* mChannelType */
-				2,			/* mDevAddress */
-				4,			/* mDevFunction */
-				HotplugDisabled,	/* mHotplug */
-				PcieGenMaxSupported,	/* mMaxLinkSpeed */
-				PcieGenMaxSupported,	/* mMaxLinkCap */
-				AspmL0sL1,		/* mAspm */
-				PCIE_2_RST,		/* mResetId */
-				0)			/* mClkPmSupport */
-	},
-	/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortDisabled,		/* mPortPresent */
-				ChannelTypeExt6db,	/* mChannelType */
-				2,			/* mDevAddress */
-				5,			/* mDevFunction */
-				HotplugDisabled,	/* mHotplug */
-				PcieGenMaxSupported,	/* mMaxLinkSpeed */
-				PcieGenMaxSupported,	/* mMaxLinkCap */
-				AspmL0sL1,		/* mAspm */
-				PCIE_3_RST,		/* mResetId */
-				0)			/* mClkPmSupport */
-	},
-};
-static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = (void *)PortListNoBayhub,
-	.DdiLinkList  = (void *)DdiList
-};
-
 /*---------------------------------------------------------------------------*/
 /**
  *  OemCustomizeInitEarly
@@ -243,9 +151,4 @@ VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 	InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
 	InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
 
-	/* Completely disable Bayhub EMMC bridge on Proto with board_id 0 */
-	/* Todo: Remove when we're done with Proto */
-	if (board_id() == 0)
-		InitEarly->GnbConfig.PcieComplexList = (void *)&PcieNoBayhub;
-
 }