diff options
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/gpio.c | 19 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/ramstage.c | 2 |
2 files changed, 18 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index aa86932426..ef80800558 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -8,8 +8,6 @@ static const struct pad_config gpio_table[] = { /* A8 : PEN_GARAGE_DET_L (wake) */ PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A16 : EMR_GARAGE_DET (notification) */ @@ -130,6 +128,23 @@ const struct pad_config *variant_early_gpio_table(size_t *num) return early_gpio_table; } +/* Set the FPMCU SPI CS line very late to workaround + * leakage of this line onto the VDD of the MCU. + */ +static const struct pad_config finalize_gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), +}; + +/* + * GPIOs configured during the mainboard finalize + */ +const struct pad_config *variant_finalize_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(finalize_gpio_table); + return finalize_gpio_table; +} + /* * Default GPIO settings before entering non-S5 sleep states. * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c index 176527b363..e861cfb34b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/ramstage.c +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -5,7 +5,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> -void variant_ramstage_init(void) +void variant_final(void) { /* * Enable power to FPMCU, wait for power rail to stabilize, |