diff options
Diffstat (limited to 'src/mainboard/google/hatch')
3 files changed, 24 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index ade12c5806..d7acbd71e7 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -21,7 +21,14 @@ chip soc/intel/cannonlake }" # USB configuration - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "{ .enable = 1, .ocpin = OC1, diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index e2380f4460..f5e85bde23 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -21,7 +21,14 @@ chip soc/intel/cannonlake }" # USB configuration - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "{ .enable = 1, .ocpin = OC1, diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d869b28a33..31efc4a1d9 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -24,7 +24,14 @@ chip soc/intel/cannonlake # NOTE: This only applies to Puff, # usb2_ports[1] and usb2_ports[3] were swapped on # reference schematics after Puff has been built. - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[2]" = "{ .enable = 1, |