diff options
Diffstat (limited to 'src/mainboard/google/hatch')
9 files changed, 576 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 512d3106c3..2bb878491b 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -99,6 +99,7 @@ config MAINBOARD_PART_NUMBER default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE @@ -123,6 +124,7 @@ config VARIANT_DIR default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU + default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 785e2c88f8..207ba2afe5 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -44,6 +44,13 @@ config BOARD_GOOGLE_MUSHU select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 +config BOARD_GOOGLE_PALKIA + bool "-> Palkia" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 + config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/palkia/Makefile.inc b/src/mainboard/google/hatch/variants/palkia/Makefile.inc new file mode 100644 index 0000000000..b0a69da366 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/Makefile.inc @@ -0,0 +1,15 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Palkia. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_SOURCES = LP_8G_2133 # 0b0000 +SPD_SOURCES += LP_16G_2133 # 0b0001 + +romstage-y += memory.c +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c new file mode 100644 index 0000000000..73868f7246 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A18 : ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A22 : ISH_GP4 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : ISH_GP5 ==> NC */ + PAD_NC(GPP_A23, NONE), + + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK ==> NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO ==> NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_NC(GPP_B22, NONE), + + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C4 : TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), + /* C7 : GPP_C7 ==> Touchscreen_INT_L */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), + /* C11 : UART0_CTS# ==> NC */ + PAD_NC(GPP_C11, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + + /* D16 : USI_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + + /* F0 : GPP_F0 ==> NC */ + PAD_NC(GPP_F0, NONE), + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : GPP_F3 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : GPP_F10 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + + /* G0 : GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), + + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : Touchscreen I2C2_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : Touchscreen I2C2_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..c9b4fb3421 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define DPTF_CPU_PASSIVE 0 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery Charger" +#define DPTF_TSR0_PASSIVE 59 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "5V Regulator" +#define DPTF_TSR1_PASSIVE 0 +#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_ACTIVE_AC0 42 +#define DPTF_TSR1_ACTIVE_AC1 41 +#define DPTF_TSR1_ACTIVE_AC2 39 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 0 +#define DPTF_TSR2_CRITICAL 65 + +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "CPU" +#define DPTF_TSR3_PASSIVE 44 +#define DPTF_TSR3_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 70, 50, 50, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on TSR3 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on TSR0 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 64000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h new file mode 100644 index 0000000000..454c8d01f2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h new file mode 100644 index 0000000000..aaf6f4d433 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c new file mode 100644 index 0000000000..1a4bf383e0 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Palkia. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/cnl_memcfg_init.h> +#include <string.h> +#include <variant/gpio.h> + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the SoC pins to the lpddr3 pins + * for both channels. + * + * "The index of the array is CPU byte number, the values are DRAM byte + * numbers." - doc #573387 + * + * the index = pin number on SoC + * the value = pin number on lpddr3 part + */ + .dqs_map[DDR_CH0] = {4, 7, 5, 6, 0, 3, 2, 1}, + .dqs_map[DDR_CH1] = {0, 3, 2, 1, 4, 7, 6, 5}, + + .dq_map[DDR_CH0] = { + {0xf0, 0xf}, + {0x0, 0xf}, + {0xf0, 0xf}, + {0xf0, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + + /* Palkia uses 200, 80.6 and 162 rcomp resistors */ + .rcomp_resistor = {200, 81, 162}, + + /* Palkia Rcomp target values */ + .rcomp_targets = {100, 40, 40, 23, 40}, + + /* Set CaVref config to 0 for LPDDR3 */ + .vref_ca_config = 0, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb new file mode 100644 index 0000000000..0792b9607d --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -0,0 +1,192 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "64" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "usb2_ports[2]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD + + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | 2nd Touchscreen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + .data_hold_time_ns = 330, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Micro SD Card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + # No Right Tpype-C port + device usb 3.1 off end + end + chip drivers/usb/acpi + register "desc" = ""Micro SD card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + end + end + end + + # Native SD Card interface unused + device pci 14.5 off end + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen USI"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C 1 + + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9009"" + register "generic.desc" = ""ELAN Touchscreen USI"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C 2 + + # I2C #3 unused + device pci 15.3 off end + + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Left Speaker Amp"" + register "uid" = "0" + register "name" = ""TL"" + device i2c 38 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Right Speaker Amp"" + register "uid" = "1" + register "name" = ""TR"" + device i2c 39 on end + end + end #I2C #4 + # GSPI #1 unused + device pci 1e.3 off end + + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel I2S + end +end |