1 files changed, 100 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
new file mode 100644
index 0000000000..d5e2e5afb5
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -0,0 +1,100 @@
+chip soc/intel/cannonlake
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+		[PchSerialIoIndexSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| I2C0              | RFU                       |
+	#| I2C2              | PS175                     |
+	#| I2C3              | MST                       |
+	#| I2C4              | Audio                     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 0,
+			.fall_time_ns = 0,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 0,
+			.fall_time_ns = 0,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 0,
+			.fall_time_ns = 0,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 0,
+			.fall_time_ns = 0,
+		},
+	}"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "vSD3_CD_B"
+
+	device domain 0 on
+		device pci 15.0 off
+			# RFU - Reserved for Future Use.
+		end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 on
+#			chip drivers/i2c/generic
+#				register "name" = ""PS175""
+#				register "desc" = ""PCON PS175""
+#				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+#				register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)"
+#				register "has_power_resource" = "1"
+#				device i2c 15 on end
+#			end
+		end # I2C #2
+		device pci 15.3 on
+#			chip drivers/i2c/generic
+#				register "name" = ""RTD21""
+#				register "desc" = ""Realtek RTD2142""
+#				device i2c 4a on end
+#			end
+		end # I2C #3
+		device pci 19.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Realtek RT5682""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
+				register "property_count" = "1"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end #I2C #4
+		device pci 1e.3 off end # GSPI #1
+	end
+
+end