diff options
Diffstat (limited to 'src/mainboard/google/guybrush/variants')
4 files changed, 67 insertions, 16 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 0720bc295a..c9b533eb5e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -199,16 +199,6 @@ static const struct soc_amd_gpio early_gpio_table[] = { /* WWAN_RST_L */ PAD_GPO(GPIO_24, LOW), -/* Enable ESPI, GSC Interrupt & I2C Communication */ - /* Unused */ - PAD_NC(GPIO_3), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Enable UART 0 */ /* UART0_RXD */ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), @@ -237,6 +227,15 @@ static const struct soc_amd_gpio espi_gpio_table[] = { PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), }; +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + /* Power-on timing requirements: * Fibocom 350-GL: * FCP0# goes high (GPIO 6) to Reset# high (GPIO 24): 20ms min @@ -353,3 +352,9 @@ const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) *size = ARRAY_SIZE(espi_gpio_table); return espi_gpio_table; } + +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 0dc6c7b4d7..b50a5901b4 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -43,6 +43,9 @@ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + bool variant_has_pcie_wwan(void); void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index e90f4a3a89..fe2dcd117e 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -44,10 +44,6 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { static const struct soc_amd_gpio override_early_gpio_table[] = { /* BID == 1: SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Unused */ - PAD_NC(GPIO_85), }; /* This table is used by guybrush variant with board version < 2. */ @@ -56,6 +52,15 @@ static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { PAD_GPO(GPIO_70, HIGH), }; +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -92,3 +97,9 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) return NULL; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index a2a0e93f46..00fd9642fd 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -39,8 +39,6 @@ static const struct soc_amd_gpio bid2_override_gpio_table[] = { }; static const struct soc_amd_gpio override_early_gpio_table[] = { - /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_NC(GPIO_18), }; @@ -48,6 +46,27 @@ static const struct soc_amd_gpio override_pcie_gpio_table[] = { PAD_NC(GPIO_18), }; + +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -72,3 +91,16 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) *size = ARRAY_SIZE(override_pcie_gpio_table); return override_pcie_gpio_table; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_tpm_gpio_table); + return bid1_tpm_gpio_table; + } + + *size = ARRAY_SIZE(bid2_tpm_gpio_table); + return bid2_tpm_gpio_table; +} |