summaryrefslogtreecommitdiff
path: root/src/mainboard/google/gru
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/google/gru')
-rw-r--r--src/mainboard/google/gru/mainboard.c39
1 files changed, 30 insertions, 9 deletions
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index dd986c4348..d1ce1649ca 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -245,39 +245,60 @@ static void usb_power_cycle(int port)
static void setup_usb(void)
{
- /* A few magic PHY tuning values that improve eye diagram amplitude
- * and make it extra sure we get reliable communication in firmware. */
- /* Set max ODT compensation voltage and current tuning reference. */
+ /*
+ * A few magic PHY tuning values that improve eye diagram amplitude
+ * and make it extra sure we get reliable communication in firmware
+ * Set max ODT compensation voltage and current tuning reference.
+ */
write32(&rk3399_grf->usbphy0_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
write32(&rk3399_grf->usbphy1_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) {
- /* Set max pre-emphasis level, only on Kevin PHY0 and PHY1 */
+ /* Set max pre-emphasis level, only on Kevin PHY0 and PHY1. */
write32(&rk3399_grf->usbphy0_ctrl[12],
RK_CLRSETBITS(0xffff, 0xa7));
write32(&rk3399_grf->usbphy1_ctrl[12],
RK_CLRSETBITS(0xffff, 0xa7));
- /* Disable the pre-emphasize in eop state and chirp
+ /*
+ * Disable the pre-emphasize in eop state and chirp
* state to avoid mis-trigger the disconnect detection
- * and also avoid high-speed handshake fail */
+ * and also avoid high-speed handshake fail for PHY0
+ * and PHY1 consist of otg-port and host-port.
+ */
write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3));
write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3));
write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3));
write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3));
- /* ODT auto compensation bypass, set max driver strength */
+ /*
+ * ODT auto compensation bypass, and set max driver
+ * strength only for PHY0 and PHY1 otg-port.
+ */
write32(&rk3399_grf->usbphy0_ctrl[2],
RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
write32(&rk3399_grf->usbphy1_ctrl[2],
RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
- /* ODT auto refresh bypass, and set the max
- * bias current tuning reference */
+ /*
+ * ODT auto refresh bypass, and set the max bias current
+ * tuning reference only for PHY0 and PHY1 otg-port.
+ */
write32(&rk3399_grf->usbphy0_ctrl[3],
RK_CLRSETBITS(0x21c, 1 << 4));
write32(&rk3399_grf->usbphy1_ctrl[3],
RK_CLRSETBITS(0x21c, 1 << 4));
+
+ /*
+ * ODT auto compensation bypass, and set default driver
+ * strength only for PHY0 and PHY1 host-port.
+ */
+ write32(&rk3399_grf->usbphy0_ctrl[15], RK_SETBITS(1 << 10));
+ write32(&rk3399_grf->usbphy1_ctrl[15], RK_SETBITS(1 << 10));
+
+ /* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */
+ write32(&rk3399_grf->usbphy0_ctrl[16], RK_CLRBITS(1 << 9));
+ write32(&rk3399_grf->usbphy1_ctrl[16], RK_CLRBITS(1 << 9));
}
setup_usb_otg0();