diff options
Diffstat (limited to 'src/mainboard/google/glados/variants/asuka')
| -rw-r--r-- | src/mainboard/google/glados/variants/asuka/data.vbt | bin | 4608 -> 0 bytes | |||
| -rw-r--r-- | src/mainboard/google/glados/variants/asuka/devicetree.cb | 41 | ||||
| -rw-r--r-- | src/mainboard/google/glados/variants/asuka/variant.c | 25 |
3 files changed, 25 insertions, 41 deletions
diff --git a/src/mainboard/google/glados/variants/asuka/data.vbt b/src/mainboard/google/glados/variants/asuka/data.vbt Binary files differdeleted file mode 100644 index 8f2a7b0614..0000000000 --- a/src/mainboard/google/glados/variants/asuka/data.vbt +++ /dev/null diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index cddb10d11a..27bbebaa57 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -60,20 +60,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -100,19 +100,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index fdef81c5cd..75e0ea689d 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -18,10 +18,13 @@ #include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <soc/romstage.h> -void variant_memory_init_params( - MEMORY_INIT_UPD *const memory_params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -39,18 +42,12 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map[0], - sizeof(memory_params->DqByteMapCh0)); - memcpy(memory_params->DqByteMapCh1, dq_map[1], - sizeof(memory_params->DqByteMapCh1)); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(memory_params->DqsMapCpu2DramCh0)); - memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(memory_params->DqsMapCpu2DramCh1)); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } int is_dual_channel(const int spd_index) |