diff options
Diffstat (limited to 'src/mainboard/google/fizz/devicetree.cb')
-rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 488 |
1 files changed, 0 insertions, 488 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb deleted file mode 100644 index 281d65ce87..0000000000 --- a/src/mainboard/google/fizz/devicetree.cb +++ /dev/null @@ -1,488 +0,0 @@ -chip soc/intel/skylake - - # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - - # Mapping of USB port # to device - #+----------------+-------+-----------------------------------+ - #| Device | Port# | Rev | - #+----------------+-------+-----------------------------------+ - #| USB C | 1 | 2/3 | - #| USB A Rear | 2 | 2/3 | - #| USB A Front | 3 | 2/3 | - #| USB A Front | 4 | 2/3 | - #| USB A Rear | 5 | 2 on base celeron, 2/3 all others | - #| USB A Rear | 6 | 2 on base celeron, 2/3 all others | - #| Bluetooth | 7 | | - #| Daughter Board | 8 | | - #+----------------+-------+-----------------------------------+ - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - # Enable DPTF - register "dptf_enable" = "1" - - # Enable S0ix - register "s0ix_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPwrOptEnable" = "1" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - register "SendVrMbxCmd" = "1" # IMVP8 workaround - register "VmxEnable" = "1" - - # Intersil VR c-state issue workaround - # send VR mailbox command for IA/GT/SA rails - register "IslVrCmd" = "2" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | - #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 1030, - .dc_loadline = 1030, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 240, - .dc_loadline = 240, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - # Enable Root port 3(x1) for LAN. - register "PcieRpEnable[2]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - # RP 3 uses SRCCLKREQ0# - register "PcieRpClkReqNumber[2]" = "0" - # RP 3, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[2]" = "1" - # RP 3, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 - register "PcieRpClkSrcNumber[2]" = "0" - - # Enable Root port 4(x1) for WLAN. - register "PcieRpEnable[3]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[3]" = "1" - # RP 4 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[3]" = "5" - # RP 4, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[3]" = "1" - # RP 4, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 - register "PcieRpClkSrcNumber[3]" = "5" - - # Enable Root port 5(x4) for NVMe. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # RP 5 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[4]" = "1" - # RP 5, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # RP 5, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # RP 5 uses CLK SRC 1 - register "PcieRpClkSrcNumber[4]" = "1" - - # Enable Root port 9 for BtoB. - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[8]" = "1" - # RP 9 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[8]" = "2" - # RP 9, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" - # RP 9, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[8]" = "2" - - # Enable Root port 11 for BtoB. - register "PcieRpEnable[10]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[10]" = "1" - # RP 11 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[10]" = "2" - # RP 11, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[10]" = "1" - # RP 11, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[10]" = "2" - - # Enable Root port 12 for BtoB. - register "PcieRpEnable[11]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[11]" = "1" - # RP 12 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[11]" = "2" - # RP 12, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[11]" = "1" - # RP 12, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[11]" = "2" - - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC - register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM - register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug - register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C5 | Audio | - #+-------------------+---------------------------+ - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 194, - .scl_hcnt = 100, - .sda_hold = 36, - }, - }, - }" - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSpi0] = PchSerialIoPci, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoSkipInit, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - register "speed_shift_enable" = "1" - register "tdp_psyspl2" = "90" - register "psys_pmax" = "120" - register "tcc_offset" = "6" # TCC of 94C - - # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""10EC5663"" - register "name" = ""RT53"" - register "desc" = ""Realtek RT5663"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" - device i2c 13 on end - end - end # I2C #5 - device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP - device pci 1c.2 on - chip drivers/net - register "customized_leds" = "0x0fa5" - register "wake" = "GPE0_PCI_EXP" - register "device_index" = "1" - device pci 00.0 on end - end - end # PCI Express Port 3 - device pci 1c.3 on - chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 4 for WLAN - device pci 1c.4 on end # PCI Express Port 5 for NVMe - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 for 2nd LAN - chip drivers/net - register "customized_leds" = "0x0fa5" - register "device_index" = "2" - device pci 00.0 on end - end - end # PCI Express Port 9 for BtoB - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" - device spi 0 on end - end - end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end |