diff options
Diffstat (limited to 'src/mainboard/google/fizz/acpi/usb.asl')
| -rw-r--r-- | src/mainboard/google/fizz/acpi/usb.asl | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl new file mode 100644 index 0000000000..f769a20317 --- /dev/null +++ b/src/mainboard/google/fizz/acpi/usb.asl @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.RHUB.HS02) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (2) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (2) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.HS03) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (3) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (3) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.HS04) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (4) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (4) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.HS05) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (0) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (0) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.HS06) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (1) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (1) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.SS02) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (2) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (2) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.SS03) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (3) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (3) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.SS04) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (4) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (4) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.SS05) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (0) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (0) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.SS06) +{ + Method (_PS0) + { + \_SB.PCI0.LPCB.EC0.UPPS (1) + } + Method (_PS3) + { + \_SB.PCI0.LPCB.EC0.UPPC (1) + } +} |