diff options
Diffstat (limited to 'src/mainboard/google/fatcat/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/fatcat/dsdt.asl | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/src/mainboard/google/fatcat/dsdt.asl b/src/mainboard/google/fatcat/dsdt.asl index 2c714d7a0c..03882c6327 100644 --- a/src/mainboard/google/fatcat/dsdt.asl +++ b/src/mainboard/google/fatcat/dsdt.asl @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <variant/ec.h> +#include <variant/gpio.h> DefinitionBlock( "dsdt.aml", @@ -9,8 +10,33 @@ DefinitionBlock( ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 + 0x20240917 ) { - /* TODO: Add ACPI code as per board design */ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/pantherlake/acpi/southbridge.asl> + #include <soc/intel/pantherlake/acpi/tcss.asl> + } + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* ChromeOS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> } |