diff options
Diffstat (limited to 'src/mainboard/google/falco/gma.c')
-rw-r--r-- | src/mainboard/google/falco/gma.c | 156 |
1 files changed, 11 insertions, 145 deletions
diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c index f3316f4a47..4e32b289d8 100644 --- a/src/mainboard/google/falco/gma.c +++ b/src/mainboard/google/falco/gma.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include <drivers/intel/gma/i915.h> +#include <northbridge/intel/haswell/haswell.h> #include "mainboard.h" /* @@ -86,52 +87,6 @@ */ #define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) -static unsigned int *mmio; -static unsigned int graphics; -static unsigned int physbase; - -void ug1(int); -void ug2(int); -void ug22(int); -void ug3(int); - -/* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. - */ - -#define GTT_PTE_BASE (2 << 20) - -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - for(i = start; i < end; i++){ - u32 word = base + i*inc; - /* note: we've confirmed by checking - * the values that mrc does no - * useful setup before we run this. - */ - gtt_write(GTT_PTE_BASE + i * 4, word|1); - gtt_read(GTT_PTE_BASE + i * 4); - } -} - static int i915_init_done = 0; /* fill the palette. */ @@ -145,75 +100,6 @@ static void palette(void) } } -void dp_init_dim_regs(struct intel_dp *dp); -void dp_init_dim_regs(struct intel_dp *dp) -{ - struct edid *edid = &(dp->edid); - - dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8; - - dp->stride = edid->bytes_per_line; - - dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); - - dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); - - dp->hsync = (edid->ha + edid->hso - 1) | - ((edid->ha + edid->hso + edid->hspw - 1) << 16); - - dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); - - dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); - - dp->vsync = (edid->va + edid->vso - 1) | - ((edid->va + edid->vso + edid->vspw - 1) << 16); - - /* PIPEASRC is wid-1 x ht-1 */ - dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1); - - dp->pfa_pos = 0; - - dp->pfa_ctl = 0x80800000; - - dp->pfa_sz = (edid->ha << 16) | (edid->va); - - dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */ - dp->port, - dp->pipe, - dp->type, - dp->lane_count, - dp->pfa_sz, - dp->edid.phsync == '+'?1:0, - dp->edid.pvsync == '+'?1:0); - - dp->transcoder = intel_ddi_get_transcoder(dp->port, - dp->pipe); - - intel_dp_compute_m_n(dp->pipe_bits_per_pixel, - dp->lane_count, - dp->edid.pixel_clock, - dp->edid.link_clock, - &dp->m_n); - - printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride); - printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal); - printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank); - printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync); - printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal); - printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank); - printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync); - printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc); - printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos); - printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl); - printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz); - printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m); - printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n); - printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m); - printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m); - printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n); - printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags); -} - void mainboard_train_link(struct intel_dp *intel_dp) { u8 read_val; @@ -289,25 +175,14 @@ void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); } -int i915lightup(unsigned int pphysbase, unsigned int pmmio, - unsigned int pgfx, unsigned int init_fb) +int panel_lightup(struct intel_dp *dp, unsigned int init_fb) { - int must_cycle_power = 0; - struct intel_dp adp, *dp = &adp; int i; int edid_ok; int pixels = FRAME_BUFFER_BYTES/64; - mmio = (void *)pmmio; - physbase = pphysbase; - graphics = pgfx; - printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %p" - "physbase %08x\n", - (void *)graphics, mmio, physbase); - void runio(struct intel_dp *dp); - void runlinux(struct intel_dp *dp); + dp->gen = 8; // This is gen 8 which we believe is Haswell dp->is_haswell = 1; dp->DP = 0x2; @@ -332,11 +207,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio, all GTT entries point to the same page 2. Developer/Recovery mode: We do not zero out all the pages pointed to by GTT in order to avoid wasting time */ - if (init_fb) - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - else { - setgtt(0, FRAME_BUFFER_PAGES, physbase, 0); - memset((void*)graphics, 0, 4096); + if (init_fb){ + set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096); + memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096); + } else { + set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0); + memset((void*)dp->graphics, 0, 4096); } dp->address = 0x50; @@ -355,11 +231,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio, edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); - dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw); - - printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock); - - dp_init_dim_regs(dp); + compute_display_params(dp); intel_ddi_set_pipe_settings(dp); @@ -372,18 +244,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio, test_gfx(dp); - set_vbe_mode_info_valid(&dp->edid, graphics); + set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics); i915_init_done = 1; return i915_init_done; fail: printk(BIOS_SPEW, "Graphics could not be started;"); - if (0 && must_cycle_power){ - printk(BIOS_SPEW, "Turn off power and wait ..."); - gtt_write(PCH_PP_CONTROL,0xabcd0000); - udelay(600000); - gtt_write(PCH_PP_CONTROL,0xabcd000f); - } printk(BIOS_SPEW, "Returning.\n"); return 0; } |