diff options
Diffstat (limited to 'src/mainboard/google/eve')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 35 |
1 files changed, 15 insertions, 20 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 38d07426dd..db843f596a 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -116,25 +116,6 @@ chip soc/intel/skylake .dc_loadline = 430, }" - # Enable Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - register "PcieRpHotPlug[0]" = "1" - #RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - - # Enable Root port 5 with SRCCLKREQ4# - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - #RP 5 uses CLK SRC 4 - register "PcieRpClkSrcNumber[4]" = "4" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -355,12 +336,26 @@ chip soc/intel/skylake end end # I2C #4 device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end end - device ref pcie_rp5 on end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "4" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "4" + end device ref uart0 on end device ref gspi0 on chip drivers/spi/acpi |