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-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index e9daf0d00d..4011693d34 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -30,7 +30,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "HeciEnabled" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "PchPmSlpS3MinAssert" = "3" # 50ms
@@ -418,7 +417,7 @@ chip soc/intel/cannonlake
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection