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-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 302a09efe0..7238a064b4 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -39,7 +39,7 @@ chip soc/intel/cannonlake
# USB2 PHY Power gating
register "PchUsb2PhySusPgDisable" = "1"
- register "s0ix_enable" = "1"
+ register "s0ix_enable" = "true"
register "dptf_enable" = "1"
register "power_limits_config" = "{
.tdp_pl1_override = 25,