summaryrefslogtreecommitdiff
path: root/src/mainboard/google/deltaur
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/google/deltaur')
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h2
-rw-r--r--src/mainboard/google/deltaur/variants/deltan/memory.c86
-rw-r--r--src/mainboard/google/deltaur/variants/deltaur/memory.c85
3 files changed, 97 insertions, 76 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
index f5e5fb6b6d..7a4ed08f59 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
@@ -18,7 +18,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
-const struct lpddr4x_cfg *variant_memory_params(void);
+const struct mb_cfg *variant_memory_params(void);
void variant_memory_init(FSP_M_CONFIG *mem_cfg);
/* SKU ID structure */
diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c
index 2184f9b16f..09e0987ed9 100644
--- a/src/mainboard/google/deltaur/variants/deltan/memory.c
+++ b/src/mainboard/google/deltaur/variants/deltan/memory.c
@@ -5,56 +5,76 @@
#include <gpio.h>
#include <soc/romstage.h>
-static const struct mb_ddr4_cfg baseboard_memcfg = {
+static const struct mb_cfg baseboard_memcfg = {
+ .type = MEM_TYPE_DDR4,
+
/* DQ byte map */
- .dq_map = {
- [0] = {
- { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */
- { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */
- { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */
- { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */
- { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */
- { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */
- { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */
- { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */
+ .ddr4_dq_map = {
+ .ddr0 = {
+ .dq0 = { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */
+ .dq1 = { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */
+ .dq2 = { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */
+ .dq3 = { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */
+ .dq4 = { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */
+ .dq5 = { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */
+ .dq6 = { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */
+ .dq7 = { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */
},
- [1] = {
- { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */
- { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */
- { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */
- { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */
- { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */
- { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */
- { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */
- { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */
+ .ddr1 = {
+ .dq0 = { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */
+ .dq1 = { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */
+ .dq2 = { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */
+ .dq3 = { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */
+ .dq4 = { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */
+ .dq5 = { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */
+ .dq6 = { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */
+ .dq7 = { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */
},
},
/* DQS CPU<>DRAM map */
- .dqs_map = {
- { 1, 0, 1, 0, 0, 1, 1, 0 },
- { 1, 0, 1, 0, 1, 0, 1, 0 }
+ .ddr4_dqs_map = {
+ .ddr0 = {
+ .dqs0 = 1,
+ .dqs1 = 0,
+ .dqs2 = 1,
+ .dqs3 = 0,
+ .dqs4 = 0,
+ .dqs5 = 1,
+ .dqs6 = 1,
+ .dqs7 = 0,
+ },
+ .ddr1 = {
+ .dqs0 = 1,
+ .dqs1 = 0,
+ .dqs2 = 1,
+ .dqs3 = 0,
+ .dqs4 = 1,
+ .dqs5 = 0,
+ .dqs6 = 1,
+ .dqs7 = 0,
+ }
},
- .ect = 0, /* Disable Early Command Training */
+ .ect = false, /* Disable Early Command Training */
};
void variant_memory_init(FSP_M_CONFIG *mem_cfg)
{
- const struct spd_info spd_info = {
- .topology = SODIMM,
- .smbus_info[0] = {.addr_dimm0 = 0x50,
- .addr_dimm1 = 0 },
- .smbus_info[1] = {.addr_dimm0 = 0x52,
- .addr_dimm1 = 0 },
+ const struct mem_spd spd_info = {
+ .topo = MEM_TOPO_DIMM_MODULE,
+ .smbus = {
+ [0] = { .addr_dimm[0] = 0x50, },
+ [1] = { .addr_dimm[0] = 0x52, },
+ },
};
const bool half_populated = false;
- struct mb_ddr4_cfg new_board_cfg_ddr4;
+ struct mb_cfg new_board_cfg_ddr4;
memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg));
- new_board_cfg_ddr4.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED);
+ new_board_cfg_ddr4.ddr4_config.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED);
- meminit_ddr4(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated);
+ memcfg_init(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated);
}
diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c
index 68c8d0e991..f8506df54b 100644
--- a/src/mainboard/google/deltaur/variants/deltaur/memory.c
+++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c
@@ -5,59 +5,61 @@
#include <gpio.h>
#include <variant/gpio.h>
-static const struct lpddr4x_cfg baseboard_memcfg = {
+static const struct mb_cfg baseboard_memcfg = {
+ .type = MEM_TYPE_LP4X,
+
/* DQ byte map */
- .dq_map = {
- [0] = {
- { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */
- { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */
+ .lp4x_dq_map = {
+ .ddr0 = {
+ .dq0 = { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */
+ .dq1 = { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */
},
- [1] = {
- { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */
- { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */
+ .ddr1 = {
+ .dq0 = { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */
+ .dq1 = { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */
},
- [2] = {
- { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */
- { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */
+ .ddr2 = {
+ .dq0 = { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */
+ .dq1 = { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */
},
- [3] = {
- { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */
- { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */
+ .ddr3 = {
+ .dq0 = { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */
+ .dq1 = { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */
},
- [4] = {
- { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */
- { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */
+ .ddr4 = {
+ .dq0 = { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */
+ .dq1 = { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */
},
- [5] = {
- { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */
- { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */
+ .ddr5 = {
+ .dq0 = { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */
+ .dq1 = { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */
},
- [6] = {
- { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */
- { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */
+ .ddr6 = {
+ .dq0 = { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */
+ .dq1 = { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */
},
- [7] = {
- { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */
- { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */
+ .ddr7 = {
+ .dq0 = { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */
+ .dq1 = { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */
},
},
/* DQS CPU<>DRAM map */
- .dqs_map = {
- [0] = { 1, 0 }, /* DDR0_DQS[1:0] */
- [1] = { 0, 1 }, /* DDR1_DQS[1:0] */
- [2] = { 0, 1 }, /* DDR2_DQS[1:0] */
- [3] = { 1, 0 }, /* DDR3_DQS[1:0] */
- [4] = { 1, 0 }, /* DDR4_DQS[1:0] */
- [5] = { 0, 1 }, /* DDR5_DQS[1:0] */
- [6] = { 0, 1 }, /* DDR6_DQS[1:0] */
- [7] = { 1, 0 }, /* DDR7_DQS[1:0] */
+ .lp4x_dqs_map = {
+ .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */
+ .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */
+ .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */
+ .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */
+ .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */
+ .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */
+ .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */
},
- .ect = 0, /* Early Command Training */
+ .ect = false, /* Early Command Training */
};
-const struct lpddr4x_cfg *variant_memory_params(void)
+const struct mb_cfg *variant_memory_params(void)
{
return &baseboard_memcfg;
}
@@ -77,12 +79,11 @@ static int variant_memory_sku(void)
void variant_memory_init(FSP_M_CONFIG *mem_cfg)
{
- const struct lpddr4x_cfg *board_cfg = variant_memory_params();
- const struct spd_info spd_info = {
- .topology = MEMORY_DOWN,
- .md_spd_loc = SPD_CBFS,
+ const struct mb_cfg *board_cfg = variant_memory_params();
+ const struct mem_spd spd_info = {
+ .topo = MEM_TOPO_MEMORY_DOWN,
.cbfs_index = variant_memory_sku(),
};
const bool half_populated = false;
- meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated);
+ memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 07:17:16 +0000