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-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index c891e6e376..1b42dfb81a 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -133,6 +133,9 @@ chip soc/intel/jasperlake
register "DdiPortBDdc" = "1"
register "DdiPortCDdc" = "1"
+ # Enable Speed Shift Technology support
+ register "speed_shift_enable" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |