diff options
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
-rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2a0b760728..e98b686608 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -29,13 +29,13 @@ chip soc/intel/tigerlake }" register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI0] = 1, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, }" @@ -52,6 +52,22 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -87,7 +103,14 @@ chip soc/intel/tigerlake device pci 1c.7 off end # PCI Express Root Port 8 device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 device pci 1e.3 off end # GSPI 1 device pci 1f.0 on chip ec/google/chromeec |