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Diffstat (limited to 'src/mainboard/google/dedede/dsdt.asl')
-rw-r--r--src/mainboard/google/dedede/dsdt.asl8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
index dce0bf35f0..933ca1a503 100644
--- a/src/mainboard/google/dedede/dsdt.asl
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -27,6 +27,9 @@ DefinitionBlock(
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/jasperlake/acpi/southbridge.asl>
}
+
+ /* Mainboard hooks */
+ #include "acpi/mainboard.asl"
}
#if CONFIG(VARIANT_HAS_CAMERA_ACPI)
@@ -34,6 +37,11 @@ DefinitionBlock(
#include <variant/acpi/camera.asl>
#endif
+
+ /* Include Low power idle table for a short term workaround to enable
+ S0ix. Once cr50 pulse width is fixed, this can be removed. */
+ #include <soc/intel/common/acpi/lpit.asl>
+
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>