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Diffstat (limited to 'src/mainboard/google/dedede/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/dedede/dsdt.asl | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl new file mode 100644 index 0000000000..c387fd38d7 --- /dev/null +++ b/src/mainboard/google/dedede/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/acpi.h> +#include <variant/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/tigerlake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> + +} |