diff options
Diffstat (limited to 'src/mainboard/google/cyan/variants')
5 files changed, 30 insertions, 20 deletions
diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c index dab80b0cef..e516bb8446 100644 --- a/src/mainboard/google/cyan/variants/banon/romstage.c +++ b/src/mainboard/google/cyan/variants/banon/romstage.c @@ -15,11 +15,10 @@ */ #include <soc/romstage.h> -#include <chip.h> +#include <baseboard/variants.h> #include <mainboard/google/cyan/spd/spd_util.h> -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) { int ram_id = get_ramid(); @@ -45,10 +44,4 @@ void mainboard_memory_init_params(struct romstage_params *params, memory_params->PcdDramDensity = 3; memory_params->PcdDualRankDram = 0; } - - /* Update SPD data */ - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; } diff --git a/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..2a16f04d2a --- /dev/null +++ b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/romstage.h> + +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index ac5cd3b0de..88b17f5da7 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -15,7 +15,7 @@ #include <soc/ramstage.h> -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { diff --git a/src/mainboard/google/cyan/variants/terra/ramstage.c b/src/mainboard/google/cyan/variants/terra/ramstage.c index 6ef4360377..51857f9819 100644 --- a/src/mainboard/google/cyan/variants/terra/ramstage.c +++ b/src/mainboard/google/cyan/variants/terra/ramstage.c @@ -17,7 +17,7 @@ #include <boardid.h> #include <variant/onboard.h> -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void board_silicon_USB2_override(SILICON_INIT_UPD *params) { uint8_t boardid = 0; uint8_t projectid = 0; diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c index e670461ff8..8b30d69c92 100644 --- a/src/mainboard/google/cyan/variants/terra/romstage.c +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -15,11 +15,10 @@ */ #include <soc/romstage.h> -#include <chip.h> +#include <baseboard/variants.h> #include <mainboard/google/cyan/spd/spd_util.h> -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) { int ram_id = get_ramid(); @@ -45,10 +44,4 @@ void mainboard_memory_init_params(struct romstage_params *params, memory_params->PcdDramDensity = 3; memory_params->PcdDualRankDram = 0; } - - /* Update SPD data */ - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; } |