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-rw-r--r--src/mainboard/google/cyan/variants/relm/ramstage.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c
index 27f9dfa241..3fbd2aebd9 100644
--- a/src/mainboard/google/cyan/variants/relm/ramstage.c
+++ b/src/mainboard/google/cyan/variants/relm/ramstage.c
@@ -36,5 +36,13 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params)
params->Usb2Port3PerPortTxiSet = 0;
params->Usb2Port3IUsbTxEmphasisEn = 2;
params->Usb2Port3PerPortTxPeHalf = 1;
+
+ //Follow Intel recommendation to set
+ //BSW D-stepping PERPORTRXISET 2 (low strength)
+ params->D0Usb2Port0PerPortRXISet = 2;
+ params->D0Usb2Port1PerPortRXISet = 2;
+ params->D0Usb2Port2PerPortRXISet = 2;
+ params->D0Usb2Port3PerPortRXISet = 2;
+ params->D0Usb2Port4PerPortRXISet = 2;
}
}