diff options
Diffstat (limited to 'src/mainboard/google/cyan/variants/edgar/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/cyan/variants/edgar/overridetree.cb | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/edgar/overridetree.cb b/src/mainboard/google/cyan/variants/edgar/overridetree.cb new file mode 100644 index 0000000000..48b10134f7 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/overridetree.cb @@ -0,0 +1,32 @@ +chip soc/intel/braswell + + register "PcdSdcardMode" = "PCH_DISABLED" + + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "0" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbHsicPort" = "0" + + device domain 0 on + device pci 12.0 off end # 8086 0F16 - SD Port + end +end |